Section 9.4, A.6.7, Syntax 9-3
Wild case

At the end of 9.4, APPEND the following paragraph

SystemVerilog also adds the keyword inside which can be used after the parenthesized expression to indicate a set membership (see 8.19) case...inside statement. In a case...inside statement the list at the beginning of a case item consists of value ranges instead of expressions. The case expression given in parentheses shall be self-determined and evaluated exactly once before any of the lists of value ranges in the case items. Its value shall be compared with the lists using the inside set membership operator in the exact order in which the case items are given. If there is a default case item, it is ignored during this linear search. During the linear search, if the list of value ranges in one of the case items matches the case expression given in parentheses, then the statement associated with that case item shall be executed and the linear search shall terminate. If all comparisons fail and the default item is given, then the default item statement shall be executed. If the default statement is not given and all of the comparisons fail, then none of the case item statements shall be executed.

 
In A.6.7 and Syntax 9-3, REPLACE
 

case_statement ::=

[ unique_priority ] case_keyword ( expression ) case_item { case_item } endcase

| [ unique_priority ] case_keyword ( expression ) matches case_pattern_item { case_pattern_item } endcase

 
WITH
 

case_statement ::=

[ unique_priority ] case_keyword ( expression ) case_item { case_item } endcase

 |  [ unique_priority ] case_keyword ( expression ) matches case_pattern_item { case_pattern_item } endcase
 | [ unique_priority ] case ( expression ) inside case_inside_item { case_inside_item } endcase 
 
 
In A.6.7 and Syntax 9-3, ADD
 
 case_inside_item ::=
 open_range_list : statement_or_null
 | default [ : ] statement_or_null