Mantis	Summary
986	13: Errata on Verilog configurations
997	4.1.4 -- expression evaluation short circuiting
1004	5.1.13: Zero fill in ?: even if signed or x/z
1009	lists in part-selects
1010	9.7.5: Description of @*, @(*) incomplete
1041	9.5: case item expression ambiguity
1043	12.5 "Upwards name referencing" description has problems
1050	"$" ambiguity in PATHPULSE$
1052	directives within directives
1053	macro formal argument usage
1072	5.5.1 Missing cases in signedness and extension rules
1073	12.3: Is "module m(.p(p));" legal?
1074	section 7: connection of vector to gate terminal
1078	17.1.1.7 leading zeros in string format
1116	D.3-D.6: delay modes not defined
1166	Section 13.2 does not describe -incdir
1169	task/function port lists and internal block item declarations
1171	12.3.{2,3,6}, named port connections for implicit ports with same name
1172	15.1, 15.6, A.7.5.3: scalar_timing_check_expressions has redundancies
1175	Add field widths to print formats
1189	reduce arithmetic operators x-pessimism
1190	reduce relational operators x-pessimism
1220	4.11: configurations, modules, and name spaces
1257	14.5 Driving wired logic: error in Fig 14-6?
1288	6.1.3: wire delays and continuous assigns
1290	5: scheduling
1333	text macro actual argument syntax too restrictive
1364	14.2.4.4: matching 'ifnone' to state-dependent paths
1366	problems with variables as module path destinations?
1386	Problem with $ferror in 1364 section 17.2.7
1425	Type/size propagation does not stop at parens (5.5.2, V-2005)
1438	Conversion of negative real to unsigned integral type
1507	1364: special characters in strings