Mantis 1940

P1800/D3a, Section 6

Net types are not data types

In P1800/D3a,

In Section 6.2,

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6.2 Data types and data objects

SystemVerilog makes a distinction between an object and its data type. A data type is a set of values and a set of operations that can be performed on those values. Data types can be used to declare data objects or to define user-defined data types that are constructed from other data types. A data object is a named entity that has a data value associated with it, such as a parameter, a variable, or a net.

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6.2 Data types and data objects

SystemVerilog makes a distinction between an object and its data type. A data type is a set of values and a set of operations that can be performed on those values. Data types can be used to declare data objects or to define user-defined data types that are constructed from other data types. A data object is a named entity that has a data value and a data type associated with it, such as a parameter, a variable, or a net.

MOVE Section 6.10 Net types between Section 6.5 Nets and variables and 6.6 Net declarations

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6.10 Net types

There are several distinct types of nets, as shown in Table 6-2.

...(all the rest of 6.10)

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6.610 Net types

The net data types can represent physical connections between structural entities, such as gates. A net shall not store a value (except for the trireg net). Instead, its value shall be determined by the values of its drivers, such as a continuous assignment or a gate. See Clause 10 and Clause 27 for definitions of these constructs. If no driver is connected to a net, its value shall be high-impedance (z) unless the net is a trireg, in which case it shall hold the previously driven value.

There are several distinct types of nets, as shown in Table 6-2. (will actually become Table 6-1)

...(all the rest of 6.10)

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6.6 Net declarations

The net data types can represent physical connections between structural entities, such as gates. A net shall not store a value (except for the trireg net). Instead, its value shall be determined by the values of its drivers, such as a continuous assignment or a gate. See Clause 10 and Clause 27 for definitions of these constructs. If no driver is connected to a net, its value shall be high-impedance (z) unless the net is a trireg, in which case it shall hold the previously driven value.

The syntax for net declarations is given in Syntax 6-1.

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6.76 Net declarations

The net data types can represent physical connections between structural entities, such as gates. A net shall not store a value (except for the trireg net). Instead, its value shall be determined by the values of its drivers, such as a continuous assignment or a gate. See Clause 10 and Clause 27 for definitions of these constructs. If no driver is connected to a net, its value shall be high-impedance (z) unless the net is a trireg, in which case it shall hold the previously driven value.

The syntax for net declarations is given in Syntax 6-1.

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A net declaration begins with a net type that determines how the values of the nets in the declaration are resolved. The declaration can include optional information such as delay values and drive or charge strength.

If a set of nets share the same characteristics, they can be declared in the same declaration statement.

Any 4-state data type can be used to declare a net. For example:

trireg (large) logic #(0,0,0) cap1;

typedef logic [31:0] addressT;

wire addressT w1;

wire struct packed { logic ecc; logic [7:0] data; } memsig;

If a data type is not specified in the net declaration, then the data type of the net is logic.

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A net declaration begins with a net type that determines how the values of the nets in the declaration are resolved. The declaration can include optional information such as delay values, and drive or charge strength, and a data type.

If a set of nets share the same characteristics, they can be declared in the same declaration statement.

Any 4-state data type can be used to declare a net. For example:

trireg (large) logic #(0,0,0) cap1;

typedef logic [31:0] addressT;

wire addressT w1;

wire struct packed { logic ecc; logic [7:0] data; } memsig;

If a data type is not specified in the net declaration or if only a range and/or signing is specified, then the data type of the net is implicitly declared as logic. For example:

wire w; // equivalent to "wire logic v;"

wire [15:0] ww; // equivalent to "wire logic [15:0] vw;"

In Section 6.7 (Variable declarations, becomes 6.8)

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Another form of variable declaration begins with the keyword var. The data type is optional in this case. If a data type is not specified, then the data type logic shall be inferred.

var byte my_byte; // equivalent to "byte my_byte;"

var v; // equivalent to "var logic v;"

var [15:0] vw; // equivalent to "var logic [15:0] vw;"

var enum bit { clear, error } status;

input var logic data_in;

var reg r

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Another form of variable declaration begins with the keyword var. The data type is optional in this case. If a data type is not specified or if only a range and/or signing is specified, then the data type logic shall be inferred.

var byte my_byte; // equivalent to "byte my_byte;"

var v; // equivalent to "var logic v;"

var [15:0] vw; // equivalent to "var logic [15:0] vw;"

var enum bit { clear, error } status;

input var logic data_in;

var reg r

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6.8 Vector declarations

All net types and the variables reg, logic and bit are single-bit types. A declaration of any of these

types without a range specification shall be considered 1 bit wide and is known as a scalar. Multibit data

objects of these types shall be declared by specifying a range, and is known as a vector. Vectors are packed arrays of scalars (see 7.4).

6.8.1 Specifying vectors

The range specification gives addresses to the individual bits in a multibit net or reg, logic or bit vector. The most significant bit specified by the msb constant expression is the left-hand value in the range, and the least significant bit specified by the lsb constant expression is the right-hand value in the range.

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6.98 Vector declarations

All net types and the variables reg, logic and bit are single-bit types. A declaration of any of these

types without a range specification shall be considered 1 bit wide and is known as a scalar. Multibit data

objects of these types shall be declared by specifying a range, and is known as a vector. Vectors are packed arrays of scalars (see 7.4).

A data object declared as reg, logic, or bit (or as a matching user-defined type or implicitly as logic) without a range specification shall be considered 1 bit wide and is known as a scalar. A multibit data object of one of these types shall be declared by specifying a range, and is known as a vector. Vectors are packed arrays of scalars (see 7.4).

6.98.1 Specifying vectors

The range specification gives addresses to the individual bits in a multibit net or reg, reg, logic or bit vector. The most significant bit, specified by the msb constant expression, is the left-hand value in the range, and the least significant bit, specified by the lsb constant expression, is the right-hand value in the range.

In 6.98.1, CHANGE

wand w; // a scalar net of type "wand"

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wand w; // a scalar net of type "wand" net

In 6.8.2, CHANGE

6.8.2 Vector net accessibility

Vectored and scalared shall be optional advisory keywords to be used in vector net declaration. If these keywords are implemented, certain operations on vectors may be restricted. If the keyword vectored is used, bit-selects and part-selects and strength specifications may not be permitted, and the PLI may consider the object unexpanded. If the keyword scalared is used, bit-selects and part-selects of the object shall be permitted, and the PLI shall consider the object expanded.

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6.8.2 Vector net accessibility

Vectored and scalared shall be optional advisory keywords to be used in vector net declarations. If these keywords are implemented, certain operations on vector nets may be restricted. If the keyword vectored is used, bit-selects and part-selects and strength specifications may not be permitted, and the PLI may consider the object net unexpanded. If the keyword scalared is used, bit-selects and part-selects of the object net shall be permitted, and the PLI shall consider the object net expanded.