Mantis 1465

P1800-2008/Draft 4

Clarify module port declaration rules

In Syntax 6-5 (6.20.1), Syntax 13-1 (13.3), and A.2.1.1
CHANGE

data_type_or_implicit ::=

data_type

| [ signing ] { packed_dimension }

TO
data_type_or_implicit ::=

data_type

| implicit_data_type [ signing ] { packed_dimension }

implicit_data_type ::= [ signing ] { packed_dimension }

In Syntax 13-2 (13.4) and A.2.6,
CHANGE
function_data_type_or_implicit ::=

function_data_type
| [ signing ] { packed_dimension }

function_data_type ::= data_type | void

TO
function_data_type_or_implicit ::=

data_type_or_void function_data_type
| implicit_data_type [ signing ] { packed_dimension }

function_data_type ::= data_type | void

In Section 13.4
CHANGE
To indicate the return type of a function, its declaration can either include an explicit function_data_type or use an implicit syntax that indicates only the ranges of the packed dimensions and, optionally, the signedness.

TO

To indicate the return type of a function, its declaration can either include an explicit function_data_type data_type_or_void or use an implicit syntax that indicates only the ranges of the packed dimensions and, optionally, the signedness.

In Syntax 17-12 (17.17), Syntax 17-13 (17.17.1), Syntax 17-18 (17.17.7) and A.6.12
CHANGE
production ::= [ function_data_type ] production_identifier [ ( tf_port_list ) ] : rs_rule { | rs_rule } ;

TO
production ::= [ data_type_or_void function_data_type ] production_identifier [ ( tf_port_list ) ] : rs_rule { | rs_rule } ;

In Syntax 34-1 and A.6.12
CHANGE
function_prototype ::= function function_data_type function_identifier ( [ tf_port_list ] )

TO
function_prototype ::= function data_type_or_void function_data_type function_identifier ( [ tf_port_list ] )

In Section 22.2.2
CHANGE

22.2.2 Port declarations

Ports provide a means of interconnecting a hardware description consisting of modules and primitives. For example, module A can instantiate module B, using port connections appropriate to module A. These port names can differ from the names of the internal nets and variables specified in the definition of module B.

TO

22.2.2 Port declarations

Ports provide a means of interconnecting a hardware description consisting of modules and primitives. For example, module A can instantiate module B, using port connections appropriate to module A. These port names can differ from the names of the internal nets and variables specified in the definition of module B.

A port can be a declaration of an interface, an event, or a variable or net of any allowed data type, including an array, a structure, or a union.
(THE PRECEDING LINE IS ALREADY MOVED TO 22.2.2 FROM 22.2.2.3 AS PART OF MANTIS 1937. THE FOLLOWING EXAMPLE IS ALSO MOVED AS PART OF MANTIS 1465, AS BEING AN EXAMPLE OF WHAT THIS SENTENCE SAYS)

typedef struct {

bit isfloat;

union { int i; shortreal f; } n;

} tagged_st; // named structure

module mh1 (input int in1, input shortreal in2, output tagged_st out);

...

endmodule

In Section 22.2.2.1
CHANGE

Each port_identifier in a port_expression in the list of ports for the module declaration shall also be declared in the body of the module as one of the following port declarations: input, output, or inout (bidirectional). This is in addition to any other data type declaration for a particular port.

TO

Each port_identifier in a port_expression in the list of ports for the module declaration shall also be declared in the body of the module as one of the following port declarations: input, output, or inout (bidirectional), ref, or as an interface port (See Clause 24). This is in addition to any net or variable declaration for a particular port_identifier. other data type declaration for a particular port.

In Section 22.2.2.3

CHANGE (AS MODIFIED BY MANTIS 1937)

22.2.2.3 Aggregate ports Rules for determining kind, data type and direction of port declarations

A port can be a declaration of an interface, an event, or a variable or net of any allowed data type, including an array, a structure, or a union. Within this subclause, the term port kind is used to mean any of the net type keywords, or the keyword var, which are used to explicitly declare a port of one of these kinds. If these keywords are omitted in a port declaration, there are default rules for determining the port kind.

typedef struct {

bit isfloat;

union { int i; shortreal f; } n;

} tagged_st; // named structure

module mh1 (input int in1, input shortreal in2, output tagged_st out);

...

endmodule

For the first port, if neither a type nor a direction is specified, then it shall be assumed to be a member of a port list, and any port direction or type declarations must be declared after the port list. If the first port kind or data type is specified, but no direction is specified, then the port direction shall default to inout. If the first port direction is specified, but no port kind or data type is specified, then the port shall default to a net of net type wire. This default net type can be changed using the ‘default_nettype compiler directive.

// Any declarations must follow the port list because first port does not

// have either a direction or type specified; Port directions default to inout

module mh4(x, y);

wire x;

tri0 y;

...

endmodule

For subsequent ports in the port list, if the direction and the port kind and data type are omitted, then the direction and any port kind and data type are inherited from the previous port. If the direction is omitted, but a port kind or data type is present, then the direction is inherited from the previous port. If the direction is present, but the port kind and data type are omitted, then the port shall default to a net of net type wire. This default net type can be changed using the ‘default_nettype compiler directive.

// second port inherits its direction and data type from previous port

module mh3 (input byte a, b);

...

endmodule

For input and inout ports, if the port kind is omitted, then the port shall default to a net of net type wire. This default net type can be changed using the `default_nettype compiler directive.

// the inout port defaults to a net of net type wire

module mh2 (inout integer a);

...

endmodule

For output ports, if the port kind is omitted, the default port kind depends on how the data type is specified. If the port is declared without the data_type syntax, then the port kind defaults to a net of the default net type. If the data type is declared with the data_type syntax, the port kind defaults to variable.

TO (INCLUDES FORMATTING CHANGE, FROM REGULAR TEXT TO DASHED ITEM LISTS)

22.2.2.3 Rules for determining kind, data type and direction of port declarations

Within this subclause, the term port kind is used to mean any of the net type keywords, or the keyword var, which are used to explicitly declare a port of one of these kinds. If these keywords are omitted in a port declaration, there are default rules for determining the port kind, as specified below.

Within this subclause, the term data type means both explicit and implicit data type declarations and does not include unpacked dimensions. An explicit data type declaration uses the data_type syntax. An implicit data type declaration uses the implicit_data_type syntax and includes only a signedness keyword and/or packed dimensions. An implicit data type declaration implies a net unless the var keyword is used. Unpacked dimensions shall not be inherited from the previous port declaration and must be repeated for each port with the same dimensions.

For the first port in the port list:

- If the direction, port kind, and data type are all omitted, then the port shall be assumed to be a member of a non-ANSI style list_of_ports, and port direction and type declarations shall be declared after the port list.

Otherwise:

- If the direction is omitted, it shall default to inout.

- If the port kind is omitted, it shall be determined as specified below.

- If the data type is omitted, it shall default to logic.

If the port kind is omitted:

- For input and inout ports, the port shall default to a net of default net type. The default net type can be changed using the ‘default_nettype compiler directive.

- For output ports, the default port kind depends on how the data type is specified:

- If the data type is omitted or declared with the implicit_data_type syntax, the port kind shall default to a net of default net type.

- If the data type is declared with the explicit data_type syntax, the port kind shall default to variable.

- A ref port is always a variable.

Examples:

// Declarations must follow the port list because the first port does not have a direction, kind, or type specified

module mh_nonansi(x, y);

input wire x;

output tri0 y;

...

endmodule

module mh0(wire x); // inout wire logic x

module mh1(integer x); // inout wire integer x

module mh2(inout integer x); // inout wire integer x

module mh3([5:0] x); // inout wire logic [5:0] x

module mh4(var x); // ERROR: direction defaults to inout, which cannot be var

module mh5(input x); // input wire logic x

module mh6(input var x); // input var logic x
module mh7(input var integer x); // input var integer x

module mh8(output x); // output wire logic x

module mh9(output var x); // output var logic x

module mh10(output signed [5:0] x); // output wire logic signed [5:0] x

module mh11(output integer x); // output var integer x

module mh12(ref [5:0] x); // ref var logic [5:0] x

module mh13(ref x [5:0]); // ref var logic x [5:0]

For subsequent ports in the port list:

- If the direction, port kind and data type are all omitted, then they shall be inherited from the previous port.

Otherwise:

- If the direction is omitted, it shall be inherited from the previous port.

- If the port kind is omitted, it shall be determined as specified above.

- If the data type is omitted, it shall default to logic.

Examples:

module mh0(wire x, y[7:0]); // inout wire logic x

// inout wire logic y[7:0]

module mh1(integer x, signed [5:0] y); // inout wire integer x

// inout wire logic signed [5:0] y

module mh3([5:0] x, wire y); // inout wire logic [5:0] x

// inout wire logic y

module mh7(input var integer x, wire y); // input var integer x

// input wire logic y

module mh9(output var x, input y); // output var logic x

// input wire logic y

module mh10(output signed [5:0] x, integer y); // output wire logic signed [5:0] x

// output var integer y

module mh12(ref [5:0] x, y); // ref var logic [5:0] x

// ref var logic [5:0] y

module mh13(ref x [5:0], y); // ref var logic x [5:0]

// ref var logic y

22.2.2.3 Aggregate ports Rules for determining kind, data type and direction of port declarations

A port can be a declaration of an interface, an event, or a variable or net of any allowed data type, including an array, a structure, or a union. Within this subclause, the term port kind is used to mean any of the net type keywords, or the keyword var, which are used to explicitly declare a port of one of these kinds. If these keywords are omitted in a port declaration, there are default rules for determining the port kind.

typedef struct {

bit isfloat;

union { int i; shortreal f; } n;

} tagged_st; // named structure

module mh1 (input int in1, input shortreal in2, output tagged_st out);

...

endmodule

For the first port, if neither a type nor a direction is specified, then it shall be assumed to be a member of a port list, and any port direction or type declarations must be declared after the port list. If the first port kind or data type is specified, but no direction is specified, then the port direction shall default to inout. If the first port direction is specified, but no port kind or data type is specified, then the port shall default to a net of net type wire. This default net type can be changed using the ‘default_nettype compiler directive.

// Any declarations must follow the port list because first port does not

// have either a direction or type specified; Port directions default to inout

module mh4(x, y);

wire x;

tri0 y;

...

endmodule

For subsequent ports in the port list, if the direction and the port kind and data type are omitted, then the direction and any port kind and data type are inherited from the previous port. If the direction is omitted, but a port kind or data type is present, then the direction is inherited from the previous port. If the direction is present, but the port kind and data type are omitted, then the port shall default to a net of net type wire. This default net type can be changed using the ‘default_nettype compiler directive.

// second port inherits its direction and data type from previous port

module mh3 (input byte a, b);

...

endmodule

For input and inout ports, if the port kind is omitted, then the port shall default to a net of net type wire. This default net type can be changed using the `default_nettype compiler directive.

// the inout port defaults to a net of net type wire

module mh2 (inout integer a);

...

endmodule

For output ports, if the port kind is omitted, the default port kind depends on how the data type is specified. If the port is declared without the data_type syntax, then the port kind defaults to a net of the default net type. If the data type is declared with the data_type syntax, the port kind defaults to variable.

In Section 23.3

CHANGE

23.3 The program construct

A typical program contains type and data declarations, subroutines, connections to the design, and one or more procedural code streams. The connection between design and testbench uses the same interconnect mechanism used to specify port connections, including interfaces.

TO

23.3 The program construct

A typical program contains type and data declarations, subroutines, connections to the design, and one or more procedural code streams. The connection between design and testbench uses the same interconnect mechanism used to specify port connections, including interfaces. Program port declaration syntax and semantics are the same as those of modules (see 22.2.2).

In Section 24.4

CHANGE

24.4 Ports in interfaces

One limitation of simple interfaces is that the nets and variables declared within the interface are only used to connect to a port with the same nets and variables. To share an external net or variable, one that makes a connection from outside of the interface as well as forming a common connection to all module ports that instantiate the interface, an interface port declaration is required. The difference between nets or variables in the interface port list and other nets or variables within the interface is that only those in the port list can be connected externally by name or position when the interface is instantiated.

TO

24.4 Ports in interfaces

One limitation of simple interfaces is that the nets and variables declared within the interface are only used to connect to a port with the same nets and variables. To share an external net or variable, one that makes a connection from outside of the interface as well as forming a common connection to all module ports that instantiate the interface, an interface port declaration is required. The difference between nets or variables in the interface port list and other nets or variables within the interface is that only those in the port list can be connected externally by name or position when the interface is instantiated. Interface port declaration syntax and semantics are the same as those of modules (see 22.2.2).