Subject: RE: Fitz's Action Items for 7/22 Meeting
From: Tom Fitzpatrick (fitz@co-design.com)
Date: Fri Jul 19 2002 - 14:17:37 PDT
Hi Adam,
Actually, you've hit on one way that an interface is different from a module
in this respect. Since the interface is only instantiated once even though
it may connect to multiple modules, or through multiple levels of hierarchy,
any logic in the interface is only executed once. Therefore, if we allowed
instantiations of OVL modules in an interface, the OVL module would execute
only once for each module instance.
-Tom
> -----Original Message-----
> From: owner-assertion@server.eda.org
> [mailto:owner-assertion@server.eda.org]On Behalf Of Adam Krolnik
> Sent: Friday, July 19, 2002 5:03 PM
> To: Tom Fitzpatrick
> Cc: sv-bc@server.eda.org; sv-ec@server.eda.org; assertion@server.eda.org
> Subject: Re: Fitz's Action Items for 7/22 Meeting
>
>
>
> Hi Tom;
>
> You wrote:
>
> >This is certainly an area that can be discussed more, since we
> may want to
> >allow OVL modules to be instantiated in interfaces, for example.
> There may
> >be a way to define what a "passive" module is in this case, and
> only allow
> >passive modules to be instantiated in interfaces. Let's discuss.
>
> Yes, we do want OVL assertion (modules) to be placed in an interface
> (in addition to Sugar assertions/SystemVerilog assertions.)
>
> But you are correct, modules with outputs (or anything driving a signal
> in
> an interface) will not work. [A signal modport'd to an input will have a
> conflict.]
>
> Extra points: Placing an assertion/OVL module in an interface will cause
> it to be
> evaluated in each place where the interface is used, correct?
>
> It would be better to only simulate an assertion/OVL module once, rather
> than
> at each usage.
>
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
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