Subject: RE: Restatement of the Sept. 4th meeting
From: Michael McNamara (mac@verisity.com)
Date: Tue Sep 03 2002 - 08:34:04 PDT
> Based on the last meeting we have scheduled a face to face meeting
> of the System Verilog Enhancement Committee for 4 September with
> the following agenda:
>
> 10:00-3:00 (with lunch provided by Synopsys) Review of Testbench
> donation analysis and recommendation. This is to include
> Overview of the capabilities in the donation supporting
> testbenches
> Detailed review and recommendations for System Verilog support
> of testbench features such as:
> Data Types
> Synchronization
> Memory Management
> Cycle-based/Clock domain
> Operators
> Methods
>
> 3:00-5:00 Discussion on System Verilog Interfaces (specific issues
> raised plus support for data channels)
>
> The meeting will be held in the Diamond Conference Room of Building B
> at:
>
> Synopsys
> 700 East Middlefield Rd.
> Mountain View, CA 94043
>
> Support for conference calling will be provided along with any hand-outs
> for the meeting being provided in email.
>
> Support for web-meeting is being investigated. Unfortunately
> video-conferencing turns out to not be possible.
>
> Details for calling in will provided closer to the meeting.
>
> Please try to attend in person. Please email the reflector if you
> intend to attend in person as this will help in sizing lunch, etc.
I will attend in person.
--
_
// Michael McNamara, Sr VP Technology <mac@verisity.com>
_ // 650-934-6888, 408-930-6875 Cell <http://www.verisity.com>
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