Subject: $sv-ec FW: BOUNCE sv-ec@eda.org: Non-member submission from [Tarak Parikh
For Vassilios.
Regards
David W. Smith
Synopsys, Inc.
Voice: 503.547.6467
-----Original Message-----
>From owner-sv-ec Wed Sep 4 08:58:26 2002
--------------10B30088934EFDE00844AD96
Vassilios,
I would like to attend if possible.
Thanks
Tarak Parikh
Vassilios.Gerousis@Infineon.Com wrote:
> I am trying to see if I can get more seats. As I said before, first
> > you please check the list.
> > C Interface Committee.
--------------10B30088934EFDE00844AD96
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Vassilios, <p>I would like to attend if possible. <p>Thanks
<p>Tarak Parikh <p>Vassilios.Gerousis@Infineon.Com wrote: <blockquote
TYPE=CITE>I am trying to see if I can get more seats. As I said before,
first respond <br>and will have first priority. <br>As it stands, we
have the following (in terms priority):
<p>1- Prakash Narain [prakash@realintent.com]
<br>2- Darrell Parham [Darrell.Parham@eng.sun.com]
<br>3- Joe Daniels
<br>4- Michael McNamara <p> If
anyone else is planning to attend. Please let me know ASAP. <p>Vassilios
<p>> -----Original Message----- <br>> From: Gerousis Vassilios (CL DAT
CS) <br>> Sent: Wednesday, September 04, 2002 6:01 AM <br>>
To: Gerousis Vassilios (CL DAT CS); 'sv-ac@eda.org';
'sv-bc@eda.org'; <br>> 'sv-cc@eda.org'; 'sv-ec@eda.org' <br>>
Cc: 'Jayant Nagda (E-mail)'; 'Grant Martin (E-mail)' <br>>
Subject: RE: Confirmed List of Attendees
and Interesting Statistics <br>> -- 23 Attendees <br>> <br>> No room in
th inn. Sorry. The meeting is closed for others. <br>>
<br>> -----Original Message-----
<br>> From: Gerousis
Vassilios (CL DAT CS) <br>>
Sent: Tuesday, September 03, 2002 12:21 PM
<br>> To:
Gerousis Vassilios (CL DAT CS); 'sv-ac@eda.org'; <br>> 'sv-bc@eda.org';
'sv-cc@eda.org'; 'sv-ec@eda.org'
<br>> Cc:
'Jayant Nagda (E-mail)'; 'Grant Martin (E-mail)'
<br>>
Subject:
RE: Confirmed List of Attendees and Interesting
<br>> Statistics -- 23 Attendees
<br>>
<br>>
<br>>
<br>> &
nbsp;
Latest Count 25 out of 25 limit
<br>>
<br>> &
nbsp;
-----Original Message-----
<br>> &
nbsp;
From: Gerousis Vassilios (CL DAT CS)
<br>> &
nbsp;
Sent: Monday, September 02, 2002 12:58 PM
<br>> &
nbsp;
To: 'sv-ac@eda.org'; 'sv-bc@eda.org'; <br>>
'sv-cc@eda.org'; 'sv-ec@eda.org'
<br>> &
nbsp;
Cc: Jayant Nagda (E-mail); Grant Martin (E-mail)
<br>> &
nbsp;
Subject: Confirmed List of
Attendees and <br>> Interesting Statistics <br>>
<br>> &
nbsp;
Confirmation of List of Attendees:
<br>>
<br>> &
nbsp;
A- Statistics:
<br>> &
nbsp; &
nbsp;
a- Number of EDA vendors: 16 attendees.
<br>> &
nbsp; &
nbsp;
b- Number of Users: 10 attendees.
<br>> &
nbsp; &
nbsp;
c- Active IEEE 1364 members: Mac could you
<br>> please check the list.
<br>> &
nbsp; &
nbsp;
d- Accellera members: 13 attendees.
<br>>
<br>> &
nbsp;
B- The List --- 25 out of 25 (cut-off number).
<br>>
<br>> &
nbsp;
1- Ambar Sarkar
<br>> ambar.sarkar@paradigm-works.com
<br>> &
nbsp;
Principal Consulting Engineer Phone: <br>>
978-824-1363
<br>> &
nbsp;
Paradigm
Works &
nbsp;
Cell:
<br>> 508-561-1868
<br>>
<br>> &
nbsp;
2- KC Chen [kchen@verplex.com]
<br>> &
nbsp;
Verplex Systems, Inc.
<br>>
<br>> &
nbsp;
3- Erich Marschner, Cadence Design Systems
<br>> &
nbsp;
Senior Architect, Advanced Verification
<br>> &
nbsp;
Phone: +1 410 750 6995 Email: erichm@cadence.com <br>>
<br>> &
nbsp;
4- David W. Smith - Synopsys -- Chairman of
<br>> SystemVerilog Enhancement Committee
<br>> &
nbsp;
Synopsys Scientist
<br>>
<br>> &
nbsp;
5- Dennis Brophy, Model Technology / Mentor Graphics
<br>> - Accellera Chairman
<br>>
<br>> &
nbsp;
6- Richard C. Ho (rho@0-in.com)
<br>> Tel: 408-487-3647
<br>>
<br>> &
nbsp;
7- Kevin Cameron [dkc@grfx.com] National
<br>> Semiconductor
<br>>
<br>> &
nbsp;
8- Bassam Tabbara [bassam@novas.com]
<br>>
<br>> &
nbsp;
9- Simon Davidmann [simond@co-design.com]
<br>>
<br>> &
nbsp;
10- Yatin Trivedi - Consultant -- Chairman of C
<br>> Interface Committee.
<br>>
<br>> &
nbsp;
11- Karen Pieper [Karen.Pieper@synopsys.com]
<br>>
<br>> &
nbsp;
12- David Fong [dfong@s3graphics.com] S3 Graphics
<br>> &
nbsp;
Design Verification Manager
<br>>
<br>> &
nbsp;
13- Grant Martin - [gmartin@cadence.com]
<br>> &
nbsp;
Fellow, Cadence
Labs
tel. +1-510-647-2804
<br>>
<br>> &
nbsp;
14- Faisal Haque - Cisco, fhaque@cisco.com - <br>>
Chairman of SystemVerilog Assertion Committee. <br>>
<br>> &
nbsp;
15- Siamak Arya [siamak@telairity.com] Telairity
<br>> Semiconductor, Inc.
<br>>
<br>> &
nbsp;
16- Jayant Nagda - Synopsys.
<br>>
<br>> &
nbsp;
17- Stephen Meier - Synopsys.
<br>>
<br>> &
nbsp;
18- Vassilios Gerousis - Infineon Technologies. -
<br>> Chairman of SystemVerilog Committeen and TCC chairman. <br>>
<br>> &
nbsp;
19- Rajeev K.
Ranjan
Rajeev Ranjan
<br>> [rajeev@realintent.com]
<br>> &
nbsp;
Director, R&D
<br>> &
nbsp;
Real Intent
<br>>
<br>> &
nbsp;
20- Kurt Takara [ktakara@0-In.com]
<br>>
<br>> &
nbsp;
21- Alec Stanculescu [alec@fintronic.com]
<br>>
<br>> &
nbsp;
22- Stuart Sutherland.
<br>> &
nbsp;
23- David Kelf
Dave Kelf <br>> [davek@co-design.com]
<br>> &
nbsp;
24- Stefenen Boyd Stefen Boyd
<br>> [stefen@boyd.com] <br>> 25-
Mehdi Mohtashemi mehdi@synopsys.com <br>> <br>> <br>>
<br>> &
nbsp;
Best Regards
<br>>
<br>> &
nbsp;
Vassilios
<br>>
<br>>
<br>>
------------------------------------------------------------------------
--
<br>> ----------------------------------------------------
<br>> &
nbsp;
Dr. Vassilios Gerousis
<br>> &
nbsp;
Chief Scientist
<br>> &
nbsp;
Infineon Technologies
<br>> &
nbsp;
DAT CS, MchB
<br>> &
nbsp;
D-81541 Munich
<br>> &
nbsp;
Germany
<br>> &
nbsp;
BalanSt. 73
<br>> &
nbsp;
Telephone: +49-89-234-21342
<br>> &
nbsp;
Fax:
+49-89-234-23650
<br>> &
nbsp;
email: Vassilios.Gerousis@infineon.com
<br>> &
nbsp;
Site Map:
<br>> <a
href="http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2
E;HNR=73">http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balans
tr%2E;HNR=73</a>
<br>>
<br>>
------------------------------------------------------------------------
--
<br>> --------------------------------------------------------
<br>>
<br>> &
nbsp;
<< File: Gerousis Vassilios (CL DAT).vcf >></blockquote>
<pre>--
Tarak
Parikh
tarak@athdl.com VP Products, @HDL,
Inc Tel : (408) 441-1317 x 111
Cell: (408) 219-4658
Fax : (408) 453-1721</pre> </html>
--------------10B30088934EFDE00844AD96--
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: Thu Sep 05 2002 - 11:20:24 PDT
From: David W. Smith (david.smith@synopsys.com)
Date: Thu Sep 05 2002 - 11:17:46 PDT
David
Synopsys Scientist
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
http://www.synopsys.com
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Sent: Wednesday, September 04, 2002 8:59 AM
To: owner-sv-ec@eda.org
Subject: BOUNCE sv-ec@eda.org: Non-member submission from [Tarak Parikh
<tarak@athdl.com>]
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To: Vassilios.Gerousis@Infineon.Com
CC: sv-ac@server.eda.org, sv-bc@server.eda.org, sv-cc@server.eda.org,
sv-ec@server.eda.org
Subject: Re: Confirmed List of Attendees and Interesting Statistics --
23
Attendees
References:
<9843A649BAD7FB4686F6FCBC840D600E02FCA641@mucse001.eu.infineon.com>
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> respond and will have first priority. As it stands, we have the
> following (in terms priority):
>
> 1- Prakash Narain [prakash@realintent.com]
> 2- Darrell Parham [Darrell.Parham@eng.sun.com]
> 3- Joe Daniels
> 4- Michael McNamara
>
> If anyone else is planning to attend. Please let me know ASAP.
>
> Vassilios
>
> > -----Original Message-----
> > From: Gerousis Vassilios (CL DAT CS)
> > Sent: Wednesday, September 04, 2002 6:01 AM
> > To: Gerousis Vassilios (CL DAT CS); 'sv-ac@eda.org';
'sv-bc@eda.org';
> > 'sv-cc@eda.org'; 'sv-ec@eda.org'
> > Cc: 'Jayant Nagda (E-mail)'; 'Grant Martin (E-mail)'
> > Subject: RE: Confirmed List of Attendees and Interesting
Statistics
> > -- 23 Attendees
> >
> > No room in th inn. Sorry. The meeting is closed for others.
> >
> > -----Original Message-----
> > From: Gerousis Vassilios (CL DAT CS)
> > Sent: Tuesday, September 03, 2002 12:21 PM
> > To: Gerousis Vassilios (CL DAT CS); 'sv-ac@eda.org';
> > 'sv-bc@eda.org'; 'sv-cc@eda.org'; 'sv-ec@eda.org'
> > Cc: 'Jayant Nagda (E-mail)'; 'Grant Martin (E-mail)'
> > Subject: RE: Confirmed List of Attendees and
Interesting
> > Statistics -- 23 Attendees
> >
> >
> >
> > Latest Count 25 out of 25 limit
> >
> > -----Original Message-----
> > From: Gerousis Vassilios (CL DAT CS)
> > Sent: Monday, September 02, 2002 12:58 PM
> > To: 'sv-ac@eda.org'; 'sv-bc@eda.org';
> > 'sv-cc@eda.org'; 'sv-ec@eda.org'
> > Cc: Jayant Nagda (E-mail); Grant Martin
(E-mail)
> > Subject: Confirmed List of Attendees
and
> > Interesting Statistics
> >
> > Confirmation of List of Attendees:
> >
> > A- Statistics:
> > a- Number of EDA vendors: 16
attendees.
> > b- Number of Users: 10 attendees.
> > c- Active IEEE 1364 members: Mac could
> > d- Accellera members: 13 attendees.
> >
> > B- The List --- 25 out of 25 (cut-off number).
> >
> > 1- Ambar Sarkar
> > ambar.sarkar@paradigm-works.com
> > Principal Consulting Engineer Phone:
> > 978-824-1363
> > Paradigm Works Cell:
> > 508-561-1868
> >
> > 2- KC Chen [kchen@verplex.com]
> > Verplex Systems, Inc.
> >
> > 3- Erich Marschner, Cadence Design Systems
> > Senior Architect, Advanced Verification
> > Phone: +1 410 750 6995 Email:
erichm@cadence.com
> >
> > 4- David W. Smith - Synopsys -- Chairman of
> > SystemVerilog Enhancement Committee
> > Synopsys Scientist
> >
> > 5- Dennis Brophy, Model Technology / Mentor
> > Graphics
> > - Accellera Chairman
> >
> > 6- Richard C. Ho (rho@0-in.com)
> > Tel: 408-487-3647
> >
> > 7- Kevin Cameron [dkc@grfx.com] National
> > Semiconductor
> >
> > 8- Bassam Tabbara [bassam@novas.com]
> >
> > 9- Simon Davidmann [simond@co-design.com]
> >
> > 10- Yatin Trivedi - Consultant -- Chairman of
> >
> > 11- Karen Pieper [Karen.Pieper@synopsys.com]
> >
> > 12- David Fong [dfong@s3graphics.com] S3
Graphics
> > Design Verification Manager
> >
> > 13- Grant Martin - [gmartin@cadence.com]
> > Fellow, Cadence Labs tel.
+1-510-647-2804
> >
> > 14- Faisal Haque - Cisco, fhaque@cisco.com
-
> > Chairman of SystemVerilog Assertion Committee.
> >
> > 15- Siamak Arya [siamak@telairity.com]
> > Telairity Semiconductor, Inc.
> >
> > 16- Jayant Nagda - Synopsys.
> >
> > 17- Stephen Meier - Synopsys.
> >
> > 18- Vassilios Gerousis - Infineon
> > Technologies. - Chairman of SystemVerilog Committeen and TCC
> > chairman.
> >
> > 19- Rajeev K. Ranjan Rajeev Ranjan
> > [rajeev@realintent.com]
> > Director, R&D
> > Real Intent
> >
> > 20- Kurt Takara [ktakara@0-In.com]
> >
> > 21- Alec Stanculescu [alec@fintronic.com]
> >
> > 22- Stuart Sutherland.
> > 23- David Kelf Dave Kelf
> > [davek@co-design.com]
> > 24- Stefenen Boyd Stefen Boyd
> > [stefen@boyd.com]
> > 25- Mehdi Mohtashemi mehdi@synopsys.com
> >
> >
> >
> > Best Regards
> >
> > Vassilios
> >
> >
> > --------------------------------------------------------------------
> > ------
> > ----------------------------------------------------
> > Dr. Vassilios Gerousis
> > Chief Scientist
> > Infineon Technologies
> > DAT CS, MchB
> > D-81541 Munich
> > Germany
> > BalanSt. 73
> > Telephone: +49-89-234-21342
> > Fax: +49-89-234-23650
> > email: Vassilios.Gerousis@infineon.com
> > Site Map:
> >
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=
73
> >
> > --------------------------------------------------------------------
> > ------
> > --------------------------------------------------------
> >
> > << File: Gerousis Vassilios (CL DAT).vcf >>
--
Tarak Parikh tarak@athdl.com
VP Products, @HDL, Inc Tel : (408) 441-1317 x 111
Cell: (408) 219-4658
Fax : (408) 453-1721