Subject: Re: $sv-ec Re: SV_EC September4,02 testbench discussion presentation
From: Alec Stanculescu (alec@fintronic.com)
Date: Fri Sep 06 2002 - 14:41:03 PDT
David,
Indeed more discution is needed until we at least feel that we
understand each other.
For the purpose of clarity I will try to summarize my opinion below:
I believe that one language with one syntax is the solution. However,
this language has several "domains": hardware description, testbench,
C/C++ code, Verilog-A, etc. The concept of "domains" is not new. From
the very beginning Verilog had a "sequential domain" and a "concurrent
domain". There were statements that you could use in one domain but
not in the other.
The advantage of having all these "domains" in one language is that
the information about the entire description can be captured in one
data-base and much more efficient tools can be developed. Having a
"pretty" syntax is a good goal, but we should not feel compelled to
make System Verilog look like C++.
With respect to the Vera-Lite donation, this approach requires the
least amount of effort on the part of language designers, implementors
and users alike since the testbench was in a separate module in Vera.
Best regards,
Alec
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