Subject: $sv-ec Forwarded Message from ["David Smith"
Greetings,
The current plan is to:
I would also like to clarify some confusion that may exist around the =
1. References - based on implementation from Vera with Verilog as =
I believe we have to raise the bar on our proposals. If there is no =
I welcome your thoughts and/or reactions to this.
Regards
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: Tue Nov 12 2002 - 22:50:45 PST
From: Vassilios.Gerousis@Infineon.Com
Date: Tue Nov 12 2002 - 22:49:57 PST
I have posted a new document up on the SV-EC website at =
http://www.eda.org/sv-ec/SVTestbench.pdf . This document is the current =
state of the effort to merge the Testbench Donation and Clarification =
documents into a single document, clean-up (remove extraneous material =
and re-organize for clarity), and incorporate some of the results of the =
committees work on reviewing the open issues.
1.. map each of the sections into the 3.1 LRM
2.. merge the information into the 3.1 LRM
3.. review the sections, as available, within the committee and amend =
as required (this can include removal if so voted)
4.. update the BNF to include the new information (after all other =
review is complete)
5.. vote on the completed LRM to be passed to the full SV organization
Stu Sutherland, Mehdi Mohtashemi, and Arturo Salz are currently working =
on the details of this effort but the milestones we are working to meet =
are:
1.. December 15th for complete integration into 3.1 LRM
2.. December 31st integration of all extensions in 3.1 LRM
3.. January 15th, 2003 complete review of 3.1 LRM
4.. (continue work on integration of other sections into the 3.1 LRM - =
SV-CC, SV-AC, SV-BC)
5.. February 24th, 2003 complete 3.1 LRM (complete at DEVCON)
6.. May 1, 2003 SV 3.1 sent to Accellera board
7.. June 1, 2003 SV 3.1 standard complete
I would like to focus any detailed discussion using the LRM as it =
becomes available. Please take a look at the new document on the site to =
see if there are any significant new issues that are raised.
state of the other extensions for 3.1. The guidelines from Vassilios for =
proposals are that they should be based on existing implementations. We =
have clearly not followed this for some of the items that we have been =
discussing. I think that this has caused us to spend more time than we =
have in discussing ideas that have a real requirement but do not have a =
well-defined solution. This results in us having to go through the =
process of creating a solution - clearly not the spirit behind the =
Accellera standardization effort. Based on the original guidelines from =
Vassilios I would like to review the outstanding extensions:
described in the Testbench donation
2. Random constraints - waiting for donation from Synopsys based on =
implemenation from Vera with Verilog
3. Alias - based on creation work within committee - this is a =
relatively small extension that has taken some time to get complete
4. Process Control - Existing process control is based upon =
implementation in System Verilog and Vera. Suggestions for improvement =
have been based upon other languages but no implementation with Verilog =
or SystemVerilog.
5. Data Channels - Discussion has been based on requirements and =
proposals taken from other languages but no implementation with Verilog =
or SystemVerilog.
existing implementation of the proposal relative to Verilog or System =
Verilog then I believe we cannot make any further progress on the =
proposal. One reason for this is that we are running out of time for the =
3.1 LRM and need to make sure that we complete work on the SVT (System =
Verilog Testbench), the Random Constraints (as required by SV-AC), =
References (as required by SV-CC), and aliases (since we have completed =
voting on it) and getting all of this in the LRM.
David W. Smith
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<DIV><FONT face=3DArial size=3D2>Greetings,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I have posted a new document up on the =
SV-EC=20
website at <A=20
href=3D"http://www.eda.org/sv-ec/SVTestbench.pdf">http://www.eda.org/sv-e=
c/SVTestbench.pdf</A>=20
. This document is the current state of the effort to merge the =
Testbench=20
Donation and Clarification documents into a single document, clean-up =
(remove=20
extraneous material and re-organize for clarity), and incorporate some =
of the=20
results of the committees work on reviewing the open =
issues.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The current plan is to:</FONT></DIV>
<OL>
<LI><FONT face=3DArial size=3D2>map each of the sections into the 3.1=20
LRM</FONT></LI>
<LI><FONT face=3DArial size=3D2>merge the information into the 3.1 =
LRM</FONT></LI>
<LI><FONT face=3DArial size=3D2>review the sections, as available, =
within the=20
committee and amend as required (this can include removal if so=20
voted)</FONT></LI>
<LI><FONT face=3DArial size=3D2>update the BNF to include the new =
information=20
(after all other review is complete)</FONT></LI>
<LI><FONT face=3DArial size=3D2>vote on the completed LRM to be passed =
to the full=20
SV organization</FONT></LI></OL>
<DIV><FONT face=3DArial size=3D2>Stu Sutherland, Mehdi Mohtashemi, and =
Arturo Salz=20
are currently working on the details of this effort but the milestones =
we are=20
working to meet are:</FONT></DIV>
<OL>
<LI><FONT face=3DArial size=3D2>December 15th for complete integration =
into 3.1=20
LRM</FONT></LI>
<LI><FONT face=3DArial size=3D2>December 31st integration of all =
extensions in 3.1=20
LRM</FONT></LI>
<LI><FONT face=3DArial size=3D2>January 15th, 2003 complete review of =
3.1=20
LRM</FONT></LI>
<LI><FONT face=3DArial size=3D2>(continue work on integration of other =
sections=20
into the 3.1 LRM - SV-CC, SV-AC, SV-BC)</FONT></LI>
<LI><FONT face=3DArial size=3D2>February 24th, 2003 complete 3.1 LRM =
(complete at=20
DEVCON)</FONT></LI>
<LI><FONT face=3DArial size=3D2>May 1, 2003 SV 3.1 sent to Accellera=20
board</FONT></LI>
<LI><FONT face=3DArial size=3D2>June 1, 2003 SV 3.1 standard=20
complete</FONT></LI></OL>
<DIV><FONT face=3DArial size=3D2>I would like to focus any detailed =
discussion using=20
the LRM as it becomes available. Please take a look at the new document =
on the=20
site to see if there are any significant new issues that are=20
raised.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>I would also like to clarify some =
confusion that=20
may exist around the state of the other extensions for 3.1. The =
guidelines from=20
Vassilios for proposals are that they should be based on existing=20
implementations. We have clearly not followed this for some of the items =
that we=20
have been discussing. I think that this has caused us to spend more time =
than we=20
have in discussing ideas that have a real requirement but do not have a=20
well-defined solution. This results in us having to go through the =
process of=20
creating a solution - clearly not the spirit behind the Accellera=20
standardization effort. Based on the original guidelines from Vassilios =
I would=20
like to review the outstanding extensions:</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>1. References - based on implementation =
from Vera=20
with Verilog as described in the Testbench donation</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>2. Random constraints - waiting for =
donation from=20
Synopsys based on implemenation from Vera with Verilog</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>3. Alias - based on creation work =
within committee=20
- this is a relatively small extension that has taken some time to get=20
complete</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>4. Process Control - Existing process =
control is=20
based upon implementation in System Verilog and Vera. Suggestions for=20
improvement have been based upon other languages but no implementation =
with=20
Verilog or SystemVerilog.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>5. Data Channels - Discussion has been =
based on=20
requirements and proposals taken from other languages but no =
implementation with=20
Verilog or SystemVerilog.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>I believe we have to raise the bar on =
our=20
proposals. If there is no existing implementation of the proposal =
relative to=20
Verilog or System Verilog then I believe we cannot make any further =
progress on=20
the proposal. One reason for this is that we are running out of time for =
the 3.1=20
LRM and need to make sure that we complete work on the SVT (System =
Verilog=20
Testbench), the Random Constraints (as required by SV-AC), References =
(as=20
required by SV-CC), and aliases (since we have completed voting on it) =
and=20
getting all of this in the LRM.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>I welcome your thoughts and/or =
reactions to=20
this.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>David W. =
Smith</FONT></DIV></BODY></HTML>