Subject: Re: $sv-ec Proposal for Random Constraints for SV-extension
From: Faisal Haque (fhaque@cisco.com)
Date: Thu Nov 21 2002 - 22:56:31 PST
Adam
We certainly need to define how assertions can be identified as constraints
for stimulus generation.
Not all the assertions may be used as constraints for generation so we need
a mechanism for how
assertions can be implicated as constraints.
-Faisal
----- Original Message -----
From: "Adam Krolnik" <krolnik@lsil.com>
To: "Mehdi Mohtashemi" <Mehdi.Mohtashemi@synopsys.com>
Cc: <sv-ec@eda.org>; <sv-ac@eda.org>
Sent: Thursday, November 21, 2002 8:44 AM
Subject: Re: $sv-ec Proposal for Random Constraints for SV-extension
>
> Hi Mehdi;
>
> You wrote:
>
> "The type randc can be thought of as a short-hand for rand unique."
>
> It may be better to have a longer-hand than 'randc' for this difference in
> functionality. The keyword 'randc' is not visually distinct enough from
rand.
>
> These proposed extensions have some overlap with assertions. The SV-AC
group
> has been talking about the fact that assumptions on a set of inputs to a
> block can constitute a specification of constraints for legal stimulus
> to be applied.
>
> Maybe this proposal needs to be sync'd up with work that the SV-AC is
doing.
> For example, this proposal defines operators 'inside' and '=>', both
concepts
> which have been discussed in the SV-AC. It would be highly useful to use
> common syntax.
>
>
> Thanks.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
>
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