Subject: $sv-ec Verification phase
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Dec 06 2002 - 09:37:56 PST
After Peter's presentation on the program block and Jay's comments about
"preponed"
processes, I was wondering if it would help to look at the problem of
placing the "verification
phase" slightly differently. Since the simulator usually has to maintain
sensitivity lists for signals
for evaluating all the "@(..." statements, you could (partially) sort
the lists so that some processes
are evaluated before others. All you would need to do then is tweak the
sensitivity statement
syntax to put the sensitive process earlier on the list if it is a
verification process, e.g.:
always @+(clock) // super-sensitive
assert ...; // check data
always @(clock) begin // process data
q = d;
- the assertion would always be processed first.
While you could have more levels of sensitivity, two levels maps to
front and back of
a list so implementation might be quite easy.
Just a thought,
Kev.
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