Subject: [sv-ec] Agenda for 9 December 2002 Meeting
From: David W. Smith (dws@dolcesfogato.com)
Date: Sat Dec 07 2002 - 12:14:48 PST
There will be the normal meeting for the SV-EC committee from 11:00am
until 1:00pm PDT on Monday 9 December 2002. This will be following the
SV-CC meeting from 9-11, as usual.
Dial in Information
* PARTICIPANT CODE: 516134
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Agenda
1, Review minutes from the 25 November meeting and approve
2. Review Action items (see minutes from 25 November meeting)
3. Review Enhancement status and proposals.
Continue review of Random Constraints for approval
Discuss handling of three items from SV-BC on interfaces
The simulation cycle proposal will be added to the list of
enhancements as well.
5. Review LRM
Review chapters 3, 4, 7, 8.7, 9
Looking for the following:
clarification
problems
solutions
The first 11 chapters will be voted on with a single vote after
reviewing them.
There have been some email sent and I would like the senders to raise
the issues as we go through the appropriate chapters.
A copy of the LRM is available at:
<http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf>
http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf
6. Address any other issues before committee
Please review the information available on the website:
<http://www.eda.org/sv-ec> http://www.eda.org/sv-ec.
The documents, minutes, issues list, and enhancement lists are all
available there.
Please come prepared with questions and answers. Are time is getting
short and we have much to accomplish.
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email:
<mailto:david.smith@synopsys.com?subject=Re:%20$sv-ec%20Agenda%20for%202
5%20November%202002%20Meeting&replyto=007c01c2928f$a1c84330$6e29040a@Ram
irez> david.smith@synopsys.com
Web: <http://www.synopsys.com/> http://www.synopsys.com
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