[sv-ec] Testbench clocking note


Subject: [sv-ec] Testbench clocking note
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Dec 11 2002 - 09:05:09 PST


Good morning;

I have two comments about the section 13.10 and 13.11

For the default clocking specification, why not allow the keyword 'default'
to be a prefix of a clocking domain definition.

E.g.

default clocking bus @(posedge clk)
   ...
endclocking

The reader thus knows the default domain once they have viewed all the domains.

On the cycle delay operator, "##". It seems to me that this operator is too
visually close to the '#' (delay) operator.

We have seen several cases where users expected to use the identity operator "==="
and ended up with the comparison operator "==" simply because read almost
the same.

The proposed "##" operator also is visually similar to the delay operation and
could easily be mistyped. Thus one who intended a cycle delay
will receive a timestep delay.

E.g.

     ##5;
     send_out = 1;

     #5;
     check_results();

As an alternative, what about using the event control operator '@' which more naturally
matches counting clocking events. E.g.

     @5;
     send_out = 1;

     @5;
     check_result();

Note that this currently is a syntax error - you can't use a constant with event control.

    Thanks.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074



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