Subject: [sv-ec] Agenda for 16 December 2002 Meeting
From: David W. Smith (david.smith@synopsys.com)
Date: Fri Dec 13 2002 - 23:34:35 PST
There will be the normal meeting for the SV-EC committee from 11:00am until
1:00pm PDT on Monday 16 December 2002.
This is the last meeting of the year and the last meeting before submittal
changes to Stu for the next LRM draft. Please come prepared to make
progress.
Dial in Information
* PARTICIPANT CODE: 516134
* Toll Free Dial In Number: (877)233-7845
* International Access/Caller Paid Dial In Number: (505)766-5458
Agenda
1, Review minutes from the 9 December meeting and approve
2. Review Action items (see minutes from 9 December meeting)
3. Review Enhancement status and proposals.
Complete review of Random Constraints and approve
4. Review LRM
Review chapters 3, 4, 7, 8.7, 9
Looking for the following:
clarification
problems
solutions
The first 11 chapters will be voted on with a single vote after reviewing
them.
There have been some email sent and I would like the senders to raise the
issues as we go through the appropriate chapters.
A copy of the LRM is available at:
<http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf>
http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf
5. Address any other issues before committee
Please review the information available on the website:
<http://www.eda.org/sv-ec> http://www.eda.org/sv-ec.
The documents, minutes, issues list, and enhancement lists are all available
there.
Please come prepared with questions and answers. Are time is getting short
and we have much to accomplish.
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
<http://www.synopsys.com/> http://www.synopsys.com
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