Subject: Re: [sv-ec] Re: $wait_all/any/...
From: Alec Stanculescu (alec@fintronic.com)
Date: Fri Dec 20 2002 - 17:34:49 PST
Arturo,
> Mac,
>
> Thanks for providing such a lucid and clear explanation of event semantics.
> I have no problems with your "creative" syntax, it's clear, concise, and, I
> believe, in the spirit of Verilog. I do think that you misunderstood the exact
> semantics of wait-order. When I wrote earlier that wait-order means strictly
> in that order, I meant that all the events must occur in precisely that order,
> and no event can occur out of order. If one were to express something like
> wait_order(a, b, c, d) using the syntax you propose, we'd have to write:
>
> @( a then ( b and not (c or d) ) then (c and not d) then d);
>
Perhaps, it would be better
@ (a then b then c then d)
which would mean what we wnat it to be.
Actually, don't you want to mean: @a then (b and not (a or c or d) )
then (c and not (a or b or d) then (d and not (a or b or c).
In other words, my question is:
wait_order (a,b,c,d) should accept a,b,a,c,d, or not?
> Of course, I've just cooked up a whole lot of non-existent syntax but I hope
> this helps to explain the semantics, and the reason why this construct is
> so valuable. And, by the way, the assertions do
> provide a very simple syntax for describing a sequence of events:
> seq = a ## b ## c ## d; (or something like that)
> But, the difference is that all those expressions are clocked, whereas the
> events can be asynchronous.
>
> Arturo
Regards,
Alec
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