Subject: Re: [sv-ec] Comments on event changes CH17.html
From: Kevin Cameron (sv-xx@grfx.com)
Date: Fri Jan 10 2003 - 00:12:27 PST
Arturo Salz wrote:
>Jay is right. VCS and all other simulators (I know) will get1.
>
> Arturo
>
I remember discussing this with someone, and they said the standard
doesn't define the order because an (interpreted?) simulator debugger
can hop from thread to thread executing one statement at a time under
user control.
Kev.
>----- Original Message -----
>From: <Shalom.Bresticker@motorola.com>
>To: "Jay Lawrence" <lawrence@cadence.com>
>Cc: "Arturo Salz" <Arturo.Salz@synopsys.COM>; <sv-ec@eda.org>
>Sent: Thursday, January 09, 2003 7:58 PM
>Subject: RE: [sv-ec] Comments on event changes CH17.html
>
>
>Actually, I have heard that VCS may give you 2.
>
>Shalom
>
>
>
>
>> reg [31:0] a,b,c;
>> fork
>> begin
>> c = 1;
>> b = c;
>> end
>> begin
>> c = 2;
>> end
>> join
>>
>>What is the value of b?
>>
>>It could be either 1 or 2. Sequential code is not guaranteed to not be
>>interleaved. I don't know of a simulator that wouldn't get a 1, but is
>>legal to say 2.
>>
>>
>
>
>
>
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