Subject: [sv-ec] Scalar Definition Itime
From: Arturo Salz (Arturo.Salz@synopsys.com)
Date: Mon Jan 13 2003 - 01:32:07 PST
Action item #6 from last week's meeting was to provide better use (or term) for the term "scalar" (or handle conflict with the use of scalar in 1364).
It is unfortunate that 1364 makes such wide use of the term scalar to mean a single bit. Possibly, this is because Verilog only had one type of aggregate (bit vectors), so using scalar to denote a single bit was appropriate. However, as SystemVerilog has grown to include structs, unions, classes, packed and unpacked multi-dimensional arrays, the use of scalar to denote a single bit is perhaps less appropriate.
Nevertheless, assuming that the term scalar remains as it is defined in 1364, we need another alternative term to denote a single variable and not an aggregate (struct, class, unpacked array). For this purpose we propose the term "singular". This term would replace the few instances of the use scalar in the 3.1 LRM.
Arturo
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