Subject: [sv-ec] Comments on Chapter 9
From: Jay Lawrence (lawrence@cadence.com)
Date: Mon Jan 13 2003 - 10:16:07 PST
The following is my issues list for chapter 9, assuming we finish up the
chapter 4 stuff today.
9.1 - Reliance on an if statement as test and set
-------------------------------------------------
We should explicitly add a test and set operation if this is what is
desired.
The phrase "a single statement (not a block)" is not well-defined in
Verilog. Unless we are going to define it much more precisely it should
be removed. Trying to redefine the interuptability (sp?) is a much
larger topic than one sentence.
9.7 - "The statements can be any valid statement or block of statements
enclosed by begin ... end."
------------------------------------------------------------------------
A begin...end is already a valid statement, this is redundant. This
should just be 'valid statement.'
9.7 - "the specification of execution in source order"
------------------------------------------------------
This should be removed. It adds no more determinism and restricts
implementations. In particular, often fork/joins can be levelized into a
single process with equivalent behavior.
9.7 - use of keywords all, any, none
------------------------------------
I agree with the editor that these keywords are too common. Much
discussion has been had on the reflector, the suggestion of allowing a
count is sort of growing on me.
9.7 - join none - sub-processes do not start until parent thread blocks
-----------------------------------------------------------------------
This is another attempt at creating determinism by defining a finer
grained process execution. It should be removed.
9.9 - $wait_child()
-------------------
Why is this a system task. Perhaps a parameter or variation on the
'wait' command like wait fork;
9.9.2 - $terminate()
--------------------
Why is this a system task? Why not just extend disable as 'disable
fork;' to explicitly kill forked children?
9.9.2 - termination of simulation
---------------------------------
The paragraph begins. "By default, SystemVerilog terminates ... when all
its programs finish executing".
Is this a mentioned elsewhere? Typically simulation will finish when
there is no further activity of any kind, not just programs. What if
these are in always blocks? A sequential block should be able to wait
for its children, but it has nothing to do with when simulation
terminates.
Is this an artifact of Vera calling tf_dofinish() when integrated
through PLI?
9.9.3 - $suspend_thread
-----------------------
Regular caveat ... Why is this a system task? Can a user override it.
...
Paragraph with "#0 ... may also be called after nonblock assignements
where 0-delay is ill-advised"
Any use of zero-delay through $suspend_thread(), #0, R/W Sync callbacks
to get deterministic results is ill-advised and this just adds another
mechanism to get yourself into trouble.
What exactly is the semantic of this if it is not the same as a #0? Run
again in the current event queue? Are you defining the relationship
between other $suspended threads?
This should just be removed. It only adds to the non-determinism.
Jay
===================================
Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
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