Re: [sv-ec] Re: discrete time


Subject: Re: [sv-ec] Re: discrete time
From: Kevin Cameron (sv-xx@grfx.com)
Date: Tue Jan 14 2003 - 20:02:02 PST


> From: Shalom.Bresticker@motorola.com
>
> The user does not know, nor can he know the number of delta cycles.
> That number can depend on event ordering, and there is some randomization
> involved in the scheduling algorithm (the simulator can choose any event on the
> active event list). Furthermore, it depends on the entire set of code being
> executed, including the testbench environment, etc.

The user doesn't know because there is no mechanism to ask. I've used delta
cycle counts internally in a couple of parallel processing simulators for fixing
cross-thread synchronization issues. The randomization is within the delta, the
deltas themselves are fairly deterministic.

Anyway, the original question was about using event sequence assertions in the
absence of a specific clock - I still don't see why a clock is essential.

Kev.
 
> > We're defining extensions to the language, no reason we can't add counting
> > deltas if it makes assertions more usable.
>
> Shalom



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