Subject: Re: [sv-ec] Re: discrete time
From: dudani@us04.synopsys.com
Date: Wed Jan 15 2003 - 10:10:38 PST
One can always reuse syntax, if we are willing to change the semantics, and
use different semantics depending on where the syntax is used.
My explanation has been to clarify that the testbench requirement about
ordering of Verilog events is different from assertions.
Surrendra
At 11:39 AM 1/15/2003 -0600, you wrote:
>At 08:02 PM 1/14/2003 -0800, Kevin Cameron wrote:
>
>>Anyway, the original question was about using event sequence assertions
>>in the
>>absence of a specific clock - I still don't see why a clock is essential.
>
>
>As Kevin so rightly points out, the original debate started by Mike
>McNamara was about the use of assertion-like syntax to represent sequences
>of events. That would be possible with a Sugar 2.0 (aka PSL) syntax, and
>the requirement (assuming anyone wishes to be troubled by clear
>requirements rather than the present diabolically ad hoc approach....) is,
>so far as I'm aware, to represent the order of sequences and I don't think
>there's any requirement to quantify the time unit(s) in which the events occur.
>
>All this talk about delta's is adding unnecessary confusion. Sugar 2.0
>syntax and semantics are more than adequate for the task of representing
>sequences, timed or un-timed. Come on Surrendra, isn't it time to
>constructively embrace re-use within a language?
>
>Regards
>
>Bernard
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Surrendra A. Dudani
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email: dudani@synopsys.com
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