Subject: [sv-ec] Question regarding struct/union and Class
From: Abhijit Chakrabarty (abhijit@electra-da.com)
Date: Tue Jan 21 2003 - 23:29:06 PST
Hello,
I have been following the development of System Verilog language. I have
a couple of questions regarding user defined structures and class. I
would seriously appreciate if someone helps me to clear the confusion in
mind.
Struct/union question 1: Can there be a reg or wire type object as a
member?
Example: typedef struct {
reg a_reg; // is it legal?
wire an_wire; // is it legal?
} myStruct;
As far as I understood, an object of a struct can be assigned either in
the concurrent area or in a process (always/initial blocks), just like
logic variables, but no in both. Is this true? If this is true and
answer to question number 1 is 'Yes' then there would be possible
concurrent assignment to 'reg' and procedural assignment to 'wire' type
objects, which is not legal in Verilog. What is the resolution here?
Class question:
Since class is a superset of struct in some sence, I have the same
confusions here. But there are other issues too.
A class type object can not be used unless initialized with the 'new'
function. Does it mean that usage of class objects is not possible in
concurrent area? The idea of initializing with 'new' and then using it
sequential in nature so it seems that it can be used only in the
sequential area. Is it true? Is there any restriction on where a Class
type object can be declared?
Regards,
Abhijit
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