Subject: [sv-ec] FW: BOUNCE sv-ec@eda.org: Non-member submission from [Gordon Vreugdenhil
-----Original Message-----
>From owner-sv-ec Thu Jan 23 09:31:58 2003
Cliff, see my notes below -- this should be clarified by the official
"Clifford E. Cummings" wrote:
Correct.
> - as a matter of fact, logic was removed from SystemVerilog altogether
Remember -- this was only a straw poll. Part of the objective of doing the
> - there will be a new varport (was this the name?) type for shared
"var" is going to be a port mode in the same was as "input", etc.
> - regs are now (the/a??) default type and we can now make one or more
reg is not the default type. You will be permitted to make a
> - scalar regs do not have to be declared
Discussed but not approved.
> - multiple continuous assignments or multiple driver-assignments
Yes.
Gord.
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Subject: BOUNCE sv-ec@eda.org: Non-member submission from [Gordon
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Date: Thu, 23 Jan 2003 09:31:50 -0800
From: Gordon Vreugdenhil <gvreugde@Synopsys.COM>
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To: "Clifford E. Cummings" <cliffc@sunburst-design.com>
CC: sv-ec@server.eda.org, sv-bc@server.eda.org
Subject: Re: [sv-bc] Removal of the SystemVerilog logic data type
References: <4.3.1.0.20030123084650.00d26b30@mail.sunburst-design.com>
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minutes as well.
>
> Hi, All -
>
[...]
> Some of the highlights (lowlights?) from yesterdays meeting (according
> to my understanding?)
> - logic is not and never was a universal data type (somebody needs to
> tell Stu to change his presentation)
> yesterday (Stu needs to change his presentation)
straw poll was to draw out any final concerns from the group. After the
straw poll on removing logic, there was subsequent discussion that made a
very good case for not removing it even though it is now functionally
redundant. I don't think that the final proposal for the official vote will
suggest removing it.
> variable-like ports to replace the previous shared-port behavior of
> logic
> procedural assignments or one continuous assignment to a reg variable
single continuous assign to a reg assuming that the declaration satisfies
the constraints discussed (can't be a shared variable, etc).
> within a module must still be done to a net type
--
----------------------------------------------------------------------
Gord Vreugdenhil gvreugde@synopsys.com
Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054
Synopsys Inc., Beaverton OR