Subject: Re: [sv-ec] Clocking Domains
From: Francoise Martinolle (fm@cadence.com)
Date: Mon Jan 27 2003 - 10:57:26 PST
You can even define the skew to be applied as a parameter:
Example:
signal.skew(1ns)
signal.skew would use default skew for signal.
At 09:12 PM 1/26/2003 -0800, Kevin Cameron wrote:
>I think someone may have pointed this out at the last meeting: it says in
>section 13.6
>that clocking domains can't be declared in $root, but example 2 in 13.11
>implies
>they can be.
>
>Since example 2 uses an interface would it not make sense to allow declaration
>of the clock domain in the interface and just use it from there:
>
> module top;
> interface y;
> clocking busA @(posedge clk1); ... endclocking
> clocking busB @(negedge clk2); ... endclocking
> endinterface
> ...
> cpu cpu1 (y);
> endmodule
>
> module cpu( interface y )
> default clocking y.busA ;
> initial begin
> ## 5; // use busA => (posedge clk1)
> ...
> end
>
>I also find the idea of sampling data "1step" (or more) ahead of the clock
>a bit hard to
>swallow since it implies "optimistic" behavior, i.e. you do something
>assuming something
>else is going to happen later. Personnally I think that that behavior
>should be replaced
>by VHDL like implicit signals e.g.:
>
> <signal>.last_step // signal value delayed by one step
> <signal>.skewed // <signal> delayed by skew and sampled at the clock
>
> <signal>.stable // how long the signal has been stable
>
>The delayed signals can be generated with simple transport delays.
>".stable" isn't really
>a signal, just an attribute for use in assertions e.g.:
>
> @(clock) assert (s.stable > clock.skew);
>
>Regards,
>Kev.
>
>
>
>
>----- End Included Message -----
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