Subject: RE: [sv-ec] tf_synchronize callback
From: David W. Smith (david.smith@synopsys.com)
Date: Thu Jan 30 2003 - 10:00:03 PST
Thank you Shalom.
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
http://www.synopsys.com
-----Original Message-----
From: shalom@pobox3.mot.com [mailto:shalom@pobox3.mot.com] On Behalf Of
Shalom Bresticker
Sent: Thursday, January 30, 2003 1:11 AM
To: David W. Smith
Cc: 'Dave Rich'; 'Neil Korpusik'; sv-ec@eda.org
Subject: Re: [sv-ec] tf_synchronize callback
Try http://www.hdlcon.org/1stpl.pdf .
Shalom
"David W. Smith" wrote:
> Any suggestion on how to get a copy of the paper?RegardsDavid David W.
> Smith Synopsys ScientistSynopsys, Inc. Synopsys Technology Park
> 2025 NW Cornelius Pass Road
> Hillsboro, OR 97124
>
> Voice: 503.547.6467
> Main: 503.547.6000
> FAX: 503.547.6906
> Email: david.smith@synopsys.com
> http://www.synopsys.com
>
> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
> Dave Rich
> Sent: Wednesday, January 29, 2003 2:03 PM
> To: Neil Korpusik
> Cc: sv-ec@eda.org
> Subject: Re: [sv-ec] tf_synchronize callback
> Neil,
>
> About the HDLCon 2002 Conference Proceedings and Best Papers
> The HDLCon 2002 Proceedings include the best papers selected by the
> conference attendees, based on their technical merit and value. The
> Best Paper award was given for "The Facts and Fallacies of Verilog
> Event Scheduling", Lee Tatischeff, Rohit Rana, Charles Dawson, David
> Roberts.
>
> Dave
>
>
>
> Neil Korpusik wrote:
>
> > Hi Jay and Francoise,
> >
> > In the last SVEC face-to-face meeting I had off-line conversations
> > with both
> > of you. Francoise mentioned a problem that has been solved with
> > the way that
> > various simulators had implemented the read-write tf_synchronize()
> > PLI call.
> >
> > As I understood it there were two additional callbacks introduced
> > so that
> > the existing simulators would be backward compatible while at the
> > same time
> > allowing users to use the same PLI code with the different
> > simulators.
> >
> > Jay mentioned that there was a writeup on this and that the
> > various
> > simulator providers had implemented this capability. I have been
> > unable
> > to locate any documentation or references to this.
> >
> > Could one of you send this out to the sv-ec reflector? I believe
> > that this
> > information would be useful in the context of the discussion that
> > is
> > currently taking place on the Verilog scheduling semantics.
> >
> > Neil
> >
> >
> >
> --
> --
> Dave Rich
> Principal Engineer, CAE, VTG
> Tel: 650-584-4026
> Cell: 510-589-2625
> DaveR@Synopsys.com
>
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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