Subject: Re: [sv-ec] Email vote on var usage
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Thu Feb 06 2003 - 19:46:46 PST
My vote is:
NO on var
NO on ref
YES on &
I have two concerns with "var" and "ref". The first is creating yet
another a keyword that can have backward compatibility issues with existing
Verilog models. "var", in particular, is likely to show up in many
existing models. I know I have used it in work I have done in the
past. Second, both of these keywords are not intuitive or
self-documenting. I feel a major goal of SystemVerilog is to bridge the
gap between C/C++ programmers and hardware engineers. As much as existing
Verilog syntax will allow, the extensions we are adding to Verilog should
be intuitive to C programmers, in order to build a bridge they will use.
Stu
At 05:04 PM 2/3/2003, David W. Smith wrote:
>Please respond to the following options for use in pass by reference.
>
> __yes __no var
> __yes __no ref (substitute use of var with ref)
> __yes __no & (substitute use of var with & and move the use to
> just before the argument name - instead of before the type)
>
>Pick one. If no item has a majority then the two highest items will be
>voted on at Monday's meeting.
>
>Elligible voting members are:
>
> Arturo, Brad, Cliff, Dennis, Francoise, Jay, Karen, Kevin, Mehdi,
> Neil, Stefen, and Stu
>
>The vote will close Friday (5:00 pm pacific)
>
>Regards
>David
>
>David W. Smith
>Synopsys Scientist
>
>Synopsys, Inc.
>Synopsys Technology Park
>2025 NW Cornelius Pass Road
>Hillsboro, OR 97124
>
>Voice: 503.547.6467
>Main: 503.547.6000
>FAX: 503.547.6906
>Email: <mailto:david.smith@synopsys.com>david.smith@synopsys.com
>http://www.synopsys.com
>
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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