Subject: [sv-ec] section 10.5.3 in draft 2
From: Francoise Martinolle (fm@cadence.com)
Date: Wed Feb 12 2003 - 09:26:53 PST
David or Arturo,
I was reading more about the tasks and functions additions by the testbench and
I came across a few things which I beleive were not pointed out by the review (
unless I missed it and which may need to be changed or added.
In section 10.5.2
Minor point:
The whole new section added by ec talks about subroutine while everywhere else
we talk about task/function. We should not introduce the subroutine word
but keep
consistency within the draft.
Major point:
Old Verilog says that output and inout actual arguments values are only
changed when the
task completes (IEEE 1364 page 154, top paragraph). This means that if the
task suspends, the actual arguments do not take the new values.
When the argument is passed by reference, in SV3.1 draft 2 is not said if
the value of an argument passed by reference is propagated to
the actual argument immediately upon assignment to the formal within the
task. I seems that
it could be interpreted that way from the following sentence:
When the argument is passed by reference, both the caller an the callee
share the same representation of the
argument, so any changes made to the argument either within the caller or
the callee will be visible to each
other.
Example :
module m
reg r;
task (var x);
reg x;
begin
x = 0;
$display(" at time %d, r = %b", $time, r); //is r changed to 0?
#1;
$display("at time %d, task returns, r = %b), $time, r);
end
endtask
initial
begin
t(r);
$display("at time %d, task call completed, r = %b), $time, r);
endinitial
always @r // does this wakes up as soon as x = 1?
$display(" at time %d, r = %b", $time, r);
endmodule
If I change the declaration of x in task t to inout, do I have a change in
behaviour?
Thanks in advance for the clarification
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