Subject: Re: [sv-ec] section 10.5.3 in draft 2
From: Francoise Martinolle (fm@cadence.com)
Date: Wed Feb 12 2003 - 12:44:44 PST
At 11:23 AM 2/12/2003 -0800, Arturo Salz wrote:
>Francoise,
>
>Subroutine is a means to refer to task/function in one English word. They
>mean the same
>thing, but I find subroutine a bit more readable. If this deviation is
>deemed a serious one,
>it should be a simple matter to replace subroutine with task/function (or
>viceversa).
As I said it is a minor issue, I was just worried about keeping everything
consistent and not
using a new words in the last few paragraphs of the spec, that's all. We
have more
important issues to argue about.
>
>As for the second question regarding the semantics of "pass by reference",
>the answer to
>the question is: yes, if the declaration of the argument is changed form
>var (ref,&) to inout
>then several changes in behavior will occur. The first change is that the
>output of the $display
>statements in task t will show r as being 0 in the case of var and X in
>the case of inout (this
>may be an unintended typo in your example, but it does point out an
>important point: within
>the task x and r are aliases to the same object).
That exactly what I was trying to find by having a $display on r.
>The second change is that the execution
>order of the always block that is sensitive to r will be affected: When x
>is declared var, the
>$display in the always block executes at time 0, and when x is declared
>inout, it executes
>at time 1. I assume that the LRM description reflects that behavior.
Well, It would have been clearer if the word "immediately" was added in the
sentence
so any changes made to the argument either within the caller or the callee
will be visible to each
other.
>
> Arturo
>
>PS - There are a few minor typos in the example:
> missing ';' after module m declaration
> replace endinitial with end
> A few unterminated strings in $display calls
>----- Original Message -----
>From: <mailto:fm@cadence.com>Francoise Martinolle
>To: <mailto:sv-ec@eda.org>sv-ec@eda.org
>Sent: Wednesday, February 12, 2003 9:26 AM
>Subject: [sv-ec] section 10.5.3 in draft 2
>
>David or Arturo,
>
>I was reading more about the tasks and functions additions by the
>testbench and
>I came across a few things which I beleive were not pointed out by the
>review (
>unless I missed it and which may need to be changed or added.
>
>In section 10.5.2
>Minor point:
>The whole new section added by ec talks about subroutine while everywhere
>else
>we talk about task/function. We should not introduce the subroutine word
>but keep
>consistency within the draft.
>
>Major point:
>
>Old Verilog says that output and inout actual arguments values are only
>changed when the
>task completes (IEEE 1364 page 154, top paragraph). This means that if the
>task suspends, the actual arguments do not take the new values.
>
>When the argument is passed by reference, in SV3.1 draft 2 is not said if
>the value of an argument passed by reference is propagated to
>the actual argument immediately upon assignment to the formal within the
>task. I seems that
>it could be interpreted that way from the following sentence:
>When the argument is passed by reference, both the caller an the callee
>share the same representation of the
>argument, so any changes made to the argument either within the caller or
>the callee will be visible to each
>other.
>Example :
>module m
>reg r;
>
>task (var x);
>reg x;
>begin
> x = 0;
> $display(" at time %d, r = %b", $time, r); //is r changed to 0?
>
> #1;
> $display("at time %d, task returns, r = %b), $time, r);
>end
>endtask
>
>initial
>begin
> t(r);
> $display("at time %d, task call completed, r = %b), $time, r);
>endinitial
>
>always @r // does this wakes up as soon as x = 1?
> $display(" at time %d, r = %b", $time, r);
>endmodule
>
>If I change the declaration of x in task t to inout, do I have a change in
>behaviour?
>
>Thanks in advance for the clarification
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