Subject: [sv-ec] Reg. escaped identifiers..
From: Raghuraman R (raghu@ti.com)
Date: Thu Feb 13 2003 - 01:56:04 PST
I dont know whether this document reflects the latest version of the
Verilog syntax.
http://www.ece.uci.edu/eceware/cadence_docs/vlogref/appA.html
<IDENTIFIER>
An identifier is any sequence of letters, digits, dollar signs
($), and underscore (_) symbol, except that the first must be
a letter or the underscore; the first character may not be a digit
or $. Upper and lower case letters are considered to be different.
Identifiers may be up to 1024 characters long. Verilog-XL,
Veritime and Verifault-XL do not recognize identifier characters
beyond the 1024th as a significant part of the identifier.
Escaped identifiers start with the backslash character (\) and
may include any printable ASCII character. An escaped identifier
ends with white space. The leading backslash character is not
considered to be part of the identifier.
Assume that there is a register (reg \test/_reg ; in Verilog)
So if there is a netlist parser, which returns the name of the signal
what should it return (\test/_reg or test/_reg). The above definition
seems to say that it is the latter but if there is some other
application working on this, is it the prerogative of the application to
find whether the signal has to be escaped or not?
What is the position of vpi on this (vpi_get_str function)?
Thanks.
-- Regds,Raghuraman R ASIC Texas Instruments (India) Ltd. Phone : +91-80-5099113 http://www.india.ti.com/~raghu
* Think. *
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