Subject: Re: [sv-ec] Pass by reference
From: Dave Rich (David.Rich@synopsys.com)
Date: Thu Feb 13 2003 - 15:34:45 PST
Hi Neil,
1364-2001 section 10.2.3 is very clear on this issue. Static task
arguments retain their value between invocations and initializes like
any other static variable. Automatic task arguments have their default
initialization applied at each invocation.
BTW, I like to think of references in SystemVerilog as "hierarchical
references". So pass by reference is actually passing a hierarchical
reference. Then there is less confusion when passing a whole array as an
argument. You are passing the name of the entire array, and not a
pointer to the first element, like you would in C.
Dave
>
>Section 10.3 and 10.2
>
>We may need to get clarification from the BC committee on "output". Does this
>imply that a parameter passed to a subroutine using the "output" directionality
>has an undefined value upon entry to that subroutine?
>
>
>Neil
>
>
>
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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