[sv-ec] clarifications needed on the passing by reference argument


Subject: [sv-ec] clarifications needed on the passing by reference argument
From: Francoise Martinolle (fm@cadence.com)
Date: Tue Feb 18 2003 - 16:08:34 PST


Arturo,

We had some discussion today in the sv-cc committee about the new passing by
reference mechanism for tasks, functions and modules. We are trying to
determine if we need to support SV directC foreign functions which
SV extern declarations have passing by reference parameters.
The EC committee brought into SV3.1 the capability of passing by reference
so I need to clarify a few things:
   1. what was the primary goal of adding this to Verilog which
      is basically passed by copy? Why is this needed for the testbench?
   2. A few people actually read the section in 3.1 about passing by
      reference and still have some questions about the semantics of
      passing by reference. We need to clarify the semantics of passing
      by reference with respect to 1) when does the object value is updated
      and 2)when does the fanout propagation occurs.
      The paragraph which relates to this is:
      "When the argument is passed by reference, both the caller and the callee subroutine share the same representation
       of the argument, so any changes made to the argument either within the caller or the callee subroutine will be visible to each other."

       I am looking for a detailed description of when the changes are made
       visible and when does the propagation occurs.

       
   3. I see some inconsistency in the bnf of the task and functions. In
      In particular, I don't see the default value arguments neither in the
      function declaration or in the function prototype.
      I also do not see that the task_enable bnf allows passing by name.
      I think that the bnf adjustment to EC have been postponed to a later
      time however the bnf for task and functions is quite important for the
      directC interface as the C function declaration will be built upon the
      extern function verilog declaration.
      The cc committee is hoping to be able to build this upon the function
      prototype, this is the reason why we would like to see asap the bnf for
      function declarations, prototype and function enable settled.
      Can someone in the ec committee provide the actual bnf?
      
      
Thanks in advance,

Francoise
    '

 



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