Subject: Re: [sv-ec] disabling of single threads
From: Raghuraman R (raghu@ti.com)
Date: Tue Mar 25 2003 - 00:37:39 PST
Simon Davidmann wrote:
>
> Some day when all this Verilog stuff is history we should have a
> beerfest and explore some pretty interesting language ideas - in my
> journeys I have discovered many - but most don't fit with the current
> Verilog style - but hey - maybe its like cars - look at the new Bug or
> Mini - if you scrunch your eyes up you can see the original - maybe in a
> few years Verilog won't be Verilog any more... maybe it will be ready
> for a real overhaul, and will need a second supercharger...
Verilog is already no more like Verilog. It looks more like C++ with
some Verilog constructs. Given the road map of many of the commercial
simulators, I wonder when these constructs will be implemented, if at
all be.
-- Regds,Raghuraman R ASIC Texas Instruments (India) Ltd. Phone : +91-80-5099113 http://www.india.ti.com/~raghu
* Think. *
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