Subject: RE: [sv-ec] Topic for post-3.1: synthesizable TB components
From: David W. Smith (david.smith@synopsys.com)
Date: Thu May 15 2003 - 09:11:18 PDT
Michael,
I have added it to the post-3.1 list and will update the site next week with
it.
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
http://www.synopsys.com
-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Michael
Burns
Sent: Wednesday, May 14, 2003 1:16 PM
To: sv-ec@eda.org
Subject: [sv-ec] Topic for post-3.1: synthesizable TB components
Hi David,
I'd like to add a topic to the list for post-3.1 discussion - synthesizable
testbench components. We touched on this topic during 3.1 development when
we were discussing statically instantiated and allocated classes, but didn't
add anything to the language for it. This topic is quite important for doing
emulation and possibly formal verification.
Mike
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