Subject: [sv-ec] randcase - Verilog equivalency
From: Arturo Salz (Arturo.Salz@synopsys.com)
Date: Tue Sep 02 2003 - 10:46:48 PDT
In the last meeting, several people asked to see the equivalent Verilog code to model
the randcase statement. The following two examples show approximately the code
that users would have to write. The user-written versions are more verbose, harder to
read, and therefore more error prone.
Example 1: Simple constant weight expressions.
randcase
15: y = 1;
18: y = 2;
7: y = 3;
1: y = 4
endcase
Can be coded as
begin
int sum = 15 + 18 + 7 + 1; // 41
if( sum == 0 )
$display( "error: all zero in randcase" );
else begin
int x = $random_range( 0, sum );
if( x < 15 )
y = 1;
else if( x < 15 + 18 )
y = 2;
else if( x < 15 + 18 + 7 )
y = 3;
else
y = 4;
end
end
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Example 2: Expression weights of different types.
int a, b;
bit [11:0] c;
randcase
c * c : F(1);
a - b : F(2);
a / b : F(3);
a % c: F(4);
endcase
Can be coded as
begin
bit [11:0] tmp1;
int tmp2, tmp3, tmp4;
int sum;
tmp1 = c * c;
tmp2 = a - b;
tmp3 = a / b;
tmp4 = a % c;
sum = tmp1 + tmp2 + tmp3 + tmp4;
if( sum == 0 )
$display( "error: all zero in randcase" );
else begin
int x = $random_range( 0, sum );
if( x < tmp1 )
F(1);
else if( x < tmp1 + tmp2 )
F(2);
else if( x < tmp1 + tmp2 + tmp3 )
F(3);
else
F(4);
end
end
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Arturo
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