Subject: Re: [sv-ec] New errata - wildcard equality
From: Jonathan Bradford;Freiburg (jonathan.bradford@micronas.com)
Date: Fri Nov 28 2003 - 02:33:37 PST
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Hello Dave
if I read this correctly, it seems that the wildcard operator allows Z in
one operand to imply that a bit in the other operand is ignored altogether.
i.e.
a = 4'b0z00;
b = 4'b0000;
a =?= b is then {a[3], a[1:0]} == {b[3], b[1:0]}
If the bit position of the z in a is dynamically reassigned to ignore
another bit in b is that supposed to be synthesizeable ?
Also if b contains z, then bits in a are then ignored. The relationship is
bidirectional.
The propogation of X in the expression will not help the modelling of
procedural `if' and `case' decisions for safe (pessimistic) RTL for
synthesis, since the final `else' or `default' clause will handle the X
expression as a false and perform any assignments in those clauses as though
the expression were valid. This is made worse when casez semantics are used
to allow synthesis optimisation.
I would suggest that a semantic that allows a match for 0 or 1 but not
X nor Z as a literal in one of the operands
would be very useful for RTL design for synthesis with procedural if and
case, as a penultimate branch before the `else' or 'default' clause could
catch remaining valid values for optimisation, leaving the final 'else' or
'default' to do explicit X assignment for pessimistic RTL modelling. The
priority/unique may need a small update.
Perhaps for example a literal `v' for valid (as ? is already taken as z),
i.e.
a == 4'b0v00
a == is then 0000 or 0100 but not 0z00 nor 0x00
So in simulation the v is treated with pessimism and in synthesis the v is
treated as ignore.
Regards
Jonathan Bradford
Dave Rich wrote:
> I put this as a proposal to both the EC and BC.
>
> To be useful for design RTL, the wildcard operator must propagate Xs
> and match casez semantics. The original VERA donation did not have
> this as a consideration for design.
>
> Remove the striked text in table 7-1
>
> a equals b, X and Z values act as wild cards
> a not equals b, X and Z values act as wild cards
>
> Remove the striked text in section 7.5 and add the text in blue
>
> The wild equality operator (=?=) and inequality operator (!?=) treat X
> and Z values in a given bit position as a wildcard.
>
> The three types of equality (and inequality) operators in
> SystemVerilog behave differently when their operands contain unknown
> values (X or Z). The == and != operators result in X if any of their
> operands contains an X or Z. The === and !== check the 4-state
> explicitly, therefore, X and Z values shall either match or mismatch,
> never resulting in X. The =?= and !?= operators treatX or Z as wild
> cards that match any value, thus, they too
> never will not result in X when matched with a Z value.
>
> --
> --
> David.Rich@Synopsys.com
> Technical Marketing Consultant
> http://www.SystemVerilog.org
> tele: 650-584-4026
> cell: 510-589-2625
>
>
--____________________________________________________________________________ ____
/\ Jonathan Bradford mailto:bradford@micronas.com \/ /\/\ MICRONAS GmbH http://www.micronas.com /\/\/\ \/\/\/ Hans-Bunte-Str.19 Tel: +49 (0)761 517 2884 \/\/ D-79108 Freiburg Fax: +49 (0)761 517 2880 \/ Germany
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <body text="#000000" bgcolor="#FFFFFF"> <br>Hello Dave <p>if I read this correctly, it seems that the wildcard operator allows Z in one operand to imply that <br>a bit in the other operand is ignored altogether. <p>i.e. <br> a = 4'b0z00; <br> b = 4'b0000; <p> a =?= b is then {a[3], a[1:0]} == {b[3], b[1:0]} <p>If the bit position of the z in a is dynamically reassigned to ignore another bit in b is that supposed to be <br>synthesizeable ? <p>Also if b contains z, then bits in a are then ignored. The relationship is bidirectional. <p>The propogation of X in the expression will not help the modelling of procedural `if' and `case' decisions <br>for safe (pessimistic) RTL for synthesis, since the final `else' or `default' clause will handle the X expression as <br>a false and perform any assignments in those clauses as though the expression were valid. <br>This is made worse when casez semantics are used to allow synthesis optimisation. <p>I would suggest that a semantic that allows a match for 0 or 1 but not X nor Z as a literal in one of the operands <br>would be very useful for RTL design for synthesis with procedural if and case, as a penultimate branch <br>before the `else' or 'default' clause could catch remaining valid values for optimisation, leaving the final 'else' or <br>'default' to do explicit X assignment for pessimistic RTL modelling. The priority/unique may need a small update. <p>Perhaps for example a literal `v' for valid (as ? is already taken as z), <p>i.e. <br> a == 4'b0v00 <p> a == is then 0000 or 0100 but not 0z00 nor 0x00 <p>So in simulation the v is treated with pessimism and in synthesis the v is treated as ignore. <br> <p>Regards <p> Jonathan Bradford <br> <p>Dave Rich wrote: <blockquote TYPE=CITE>I put this as a proposal to both the EC and BC. <p>To be useful for design RTL, the wildcard operator must propagate Xs and match casez semantics. The original VERA donation did not have this as a consideration for design. <p>Remove the striked text in table 7-1 <p>a equals b, <strike><font color="#FF0000">X and </font></strike>Z values act as wild cards <br>a not equals b, <strike><font color="#FF0000">X and</font></strike> Z values act as wild cards <p>Remove the striked text in section 7.5 and add the text in <font color="#0000FF">blue</font> <p>The wild equality operator (=?=) and inequality operator (!?=) treat<font color="#FF0000"><strike> X and</strike> </font>Z values in a given bit position as a <br>wildcard. <p>The three types of equality (and inequality) operators in SystemVerilog behave differently when their operands <br>contain unknown values (X or Z). The == and != operators result in X if any of their operands contains an X or <br>Z. The === and !== check the 4-state explicitly, therefore, X and Z values shall either match or mismatch, <br>never resulting in X. The =?= and !?= operators treat<font color="#FF0000"><strike>X or</strike> </font>Z as wild cards that match any value, thus, they <strike><font color="#FF0000">too</font></strike> <br><strike><font color="#FF0000">never</font> </strike><font color="#0000FF">will not </font>result in X <font color="#0000FF">when matched with a Z value</font>. <pre cols="100" class="moz-signature">-- -- <a href="mailto:David.Rich@Synopsys.com" class="moz-txt-link-abbreviated">David.Rich@Synopsys.com </a>Technical Marketing Consultant <a href="http://www.SystemVerilog.org" class="moz-txt-link-freetext">http://www.SystemVerilog.org </a>tele: 650-584-4026 cell: 510-589-2625
</pre> </blockquote>
<pre>--
____________________________________________________________________________ ____
/\ Jonathan Bradford &n bsp; <A HREF="mailto:bradford@micronas.com">mailto:bradford@micronas.com</A> \/ /\/\ MICRONAS GmbH <A HREF="http://www.micronas.com">http://www.micronas.com> /\/\/\ \/\/\/ Hans-Bunte-Str.19   ; Tel: +49 (0)761 517 2884 \/\/ D-79108 Freiburg &n bsp; Fax: +49 (0)761 517 2880 \/ Germany</pre> </body> </html>
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