Re: [sv-ec] Ballot for Final Approval Vote

From: Francoise Martinolle <fm@cadence.com>
Date: Mon Mar 15 2004 - 09:53:41 PST

>Cadence votes YES on the following statement:

>"SV-EC accepts LRM Draft 5 as the SystemVerilog 3.1A standard and
>recommends forwarding it to the Accellera board for its approval."
>
>
Received on Mon Mar 15 09:53:51 2004

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