[sv-ec] Query regarding to design

From: Saurabh Kumar Shrimal, Noida <saurabhsk@noida.hcltech.com>
Date: Tue Sep 14 2004 - 02:03:14 PDT

Hi All,

Plz let me know any mini project in SystemVerilog 3.1a , based on Design
and Verification(Assertion) , to make the language concept more clear

Regards

SAURABH

Received on Tue Sep 14 02:03:22 2004

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