RE: [sv-ec] Errata 238 and 240 and a suggestion for a BNF change

If the suggestion is that sequences can be used in arbitrary SystemVerilog
expressions, then Surrendra is right to be concerned.

Verilog expressions are assumed to be evaluated "instantly", with no
passage of simulation time. Function calls are not allowed to have delays
for this reason. There are good reasons for this, and trying to change it
would have major impact on the language. Every context where expressions
can be used would have to be considered and possibly have its semantics
redefined. This would require a lot of work, and cannot be done lightly.

Steven Sharp
sharp@cadence.com
Received on Mon Oct 4 13:47:29 2004