RE: [sv-ec] Re: [sv-bc] question on str.putc()

BTW, let's keep this on the SV-EC for now since strings are a testbench
issues and I don't think people want to keep reading this in two
different reflectors.

I think some confusion was created when the SV-EC/SV-BC eliminated the
'char' type instead 'byte'. (Something that I still do not agree with).
Then defining a string in terms of an array of characters makes no
sense, which is what proposal 197 is trying to do.

I think it would be better to define a string as a queue of bytes, with
implicit casting rules for string literals and integral values to string
variables.

What Surrendra is trying to say is that there are no implicit casting
rules from string variables assigned to integral values, so the example
'r = a;' is illegal without an explicit cast. And 'a[0] = "hi";' should
be the same as 'a[0] = "i";' Since a[0] is an integral byte type, and
integral type rules apply, therefore the left-most 8 bits of "hi" are
truncated.

Back to the original question:

Is str.putc(j, x) semantically equivalent to str[j] = x?

I think yes, only if x is an integral value.
Otherwise str.putc(j, x)is semantically equivalent to str[j] = x[0] if x
is a string.

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Shalom.Bresticker@freescale.com
Sent: Sunday, October 17, 2004 9:01 PM
To: Surrendra Dudani
Cc: sv-bc@eda.org; sv-ec@eda.org
Subject: Re: [sv-ec] Re: [sv-bc] question on str.putc()

3.7 has the example

reg [15:0] r ;
string a ;

r = a ; // OK

If you say that assignment does not appear in Table 3-2 (String
operators),
I would say that assignment is not considered an operator.
3.6, for example, also separates assignments from operators.

If you refer to the sentence, "A string, string literal, or packed array
can be assigned to a string variable," that is referring to what can be
assigned to a string variable, not what a string can be assigned to.

Shalom

On Sun, 17 Oct 2004, Surrendra Dudani wrote:

> Below is my reasoning for the comments I made related to Shalom's
question.
>
>
> string x = "abc";
> str[2] = "abc"; (1)
> str[2] = x; (2)
>
> str[2] is a character which in SV is a byte.
> Statement (1) is a Verilog statement, so it must follow Verilog
semantics.
> Statement (2) should be illegal as an SV string variable cannot be
assigned
> directly to a byte, logic, etc.

-- 
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