RE: [sv-ec] final blocks in testbench

I suspect this as an omission in the LRM. Once you hit end-of
simulation, all the final blocks execute as a single zero-delay
sequential block. So it wouldn't make any difference to put a final
block in a module or a program. If your testbench is contained in a
single program block, it seems silly to add a module to execute a final
block.

I think it is silly that always blocks are not allowed in programs
because 'always' is the same as 'initial forever'. However, I do think
anything that you would model with an always block (like a clock
generator) belongs in a module, not a program. So this rule may just be
enforcing a modeling style.

Dave
 

> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
> Michael Burns
> Sent: Wednesday, February 23, 2005 11:13 AM
> To: sv-ec@eda.org
> Subject: [sv-ec] final blocks in testbench
> 
> 
> Hi folks,
> 
> The Accellera System Verilog 3.1a standard appears to only allow final
> blocks in modules and interfaces - not in programs. To me, this
appears
> to make it difficult to specify any end-of-simulation behavior for the
> testbench to execute in the reactive region.  Have I misinterpreted
the
> standard? Is this changed in the current p1800 draft? Is there a
better
> way to specify end-of-sim behavior for the testbench?
> 
> Thanks,
> Mike