Re: [sv-ec] assigning string literal to parameter

From: Steven Sharp <sharp_at_.....>
Date: Tue Nov 21 2006 - 10:21:28 PST

In Verilog, a string literal is just an integral constant, so it is
perfectly legal to assign to an untyped parameter.

Steven Sharp
sharp@cadence.com

Received on Tue Nov 21 10:21:37 2006

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