[sv-ec] Sequence expression

Hi,

Is this a valid sequence declaration :

sequence S;
@(posedge clk1) (state == ST1) @(posedge clk2) ##1 (ind1 && ind2);
endsequence

According to BNF:

sequence_expr ::= clocking_event sequence_expr
clocking_event ::= @ identifier

Thanks,
Sarani





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