Shalom, > The clocking event may specify both edges, as in this example from the LRM: > > clocking ck2 @(clk); // no edge specified! > default input #1step output negedge; // legal > input ... ; > output ... ; > endclocking Hmmmm..... Can anyone shed any light on what that could possibly mean? Let's try to use it... @(negedge clk) #1; // get to just after negedge @(ck2); // get to rising edge ck2.some_output <= 1'b1; // takes effect on next negedge @(ck2); // get to negedge ck2.some_output <= 1'b0; // now? one whole cycle later? Surely this is precisely the situation that the "simple edge" wording was intended to avoid, and the example must be wrong? -- Jonathan Bromley Consultant Doulos - Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com -------------------------------------------------------------------------------- Doulos Ltd is registered in England and Wales with company no. 3723454 Its registered office is 4 Brackley Close, Bournemouth International Airport, Christchurch, BH23 6SE, UK. This message may contain personal views which are not the views of Doulos, unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Aug 12 15:01:26 2009
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