[sv-ec] RE: Mantis 3028, constraints for unique array elements

I agree with Arturo on the problems caused by heterogeneous collections and maximal bit-widths.
The following:
constraint terse { unique {a, b, c}; }
should be equivalent to:
                constraint verbose { a != b; b != c; a != c; }

Going forward, this new constraint should allow the user to easily express their intent, and allow the tool to efficiently find a solution.

In all my customer discussions, I have only seen requests for unique arrays, not for unique values to unrelated variables, except for 3 or less variables.
If SystemVerilog provides a simple way to generate unique arrays, it will solve 99% of the customer needs, without adding unexpected behavior.
Tool vendors will be able to solve the array constraint faster than if it had been expressed with nested foreach loops.

Thanks!
Chris Spear

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