[sv-ec] Concurrency semantics in SystemVerilog

What assumptions can I make if I assume that a SystemVerilog simulator
may execute in a truly concurrent manner on a multiprocessor computer
system?

Section 4.6a) of the LRM states:

Execution of statements in a particular begin-end block can be
suspended in favor
of other processes in the model;

But there's a lot that one can read into that sentence. On the one
hand, it is clear that if a sequence of statements in a begin-end
block contains a blocking statement (e.g. #delay or a call to a task
that consumes time) then the execution will be suspended.

However, can execution be suspended (even on a uniprocessor) if a
sequence contains no blocking statement? The LRM doesn't say that it
won't. And on a multiprocessor, two different begin-end blocks can
execute in a truly concurrent manner. Nothing gets "suspended" in this
case.

If truly concurrent execution is possible, then what SystemVerilog
constructs, if any, can I assume will be thread-safe?

- mailboxes? (likely yes)
- x++ (I'd be surprised if this were concurrent-safe)
- queue operations such as q.push_back()
- other?

This isn't hypothetical either. Every SystemVerilog implementation
that I have access to is running on multiprocessor hardware, and I am
assuming that all EDA vendors are working on MP-aware implementations
of SV. (I am aware of such an effort from one of the "big 3".) As an
author of SystemVerilog IP I want to ensure that my code will work
properly on such systems.

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