RE: [sv-ec] input skew

Jonathan, please note Mantis 1247.

Regards,
Shalom

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Jonathan Bromley
Sent: Wednesday, June 22, 2011 11:32 AM
To: Daniel Mlynek; sv-ec@eda.org
Subject: Re: [sv-ec] input skew

h Daniel

I think you may be confusing "time unit" and "time step". However, I agree that the phrase "the time step skew time units prior" is quite hard to parse. In that phrase, "skew" is a placeholder for the value in the #skew sampling delay, so we could rewrite it as "the time step that occurred _skew_ time units prior to the clocking event".

Consequently, input#1 sets the skew to one time UNIT, whereas input#1step sets the skew to one time STEP.

The intent of #1step is to sample values as they were _immediately before_ the current moment in simulation time. Since a time step is a point in simulation time where there are some events, it's clear that there can be no activity (no value changes, no events) between the previous timestep and the current time step. So it doesn't matter at what absolute time the previous time step occurred. It could be as recent as one time-resolution before the current time, but it might be long before that.

In any case, #1step sampling requires the clocking block to sample values in Postponed of the immediately previous time step. This is exactly equivalent to sampling in the Preponed region of the current time step, because there can be no value changes in the time between those two timesteps. That's quite satisfying, because it means input#1step sampling reliably gives the same values that are seen by assertions. [Question for VPI experts: is there any way that VPI callbacks could break that equivalence?]

Another question for everyone: I used to think that there was a subtle distinction between "time slot" and "time step", but in the 2009 LRM they appear to be used interchangeably. Neither term appears in the Glossary. "time slot" is explained pretty thoroughly in clause 4, but "time step" doesn't appear to be defined anywhere. The assertions, coverage and VPI clauses seem to favour "time step", whereas clause 4 predominantly uses "time slot". Is there a case for making an editorial change to use the same term everywhere?

Jonathan Bromley
________________________________
From: Daniel Mlynek <danielm@aldec.com.pl>
To: "sv-ec@eda.org" <sv-ec@eda.org>
Sent: Wednesday, 22 June 2011, 7:52
Subject: [sv-ec] input skew

LRM senstences:
1. A 1step input skew allows input signals to sample their steady-state values in the time step immediately before the clock event (i.e., in the preceding Postponed region).
2.If the input skew is not an explicit #0, then the value sampled corresponds to the signal value at the Postponed region of the time step skew time units prior to the clocking event
sugest that #1step and #1 input skew are the same
So is clocking event occurs in time 10.
Then sampled value is taken from postponed region of time 9 in both cases
Is it how it should work If so then 1step is redunand.

DANiel

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