Re: [sv-ec] input skew

From: Jonathan Bromley <jonathan.bromley@verilab.com>
Date: Thu Jun 23 2011 - 03:33:25 PDT

On Thu, Jun 23, 2011 at 10:35 AM, Bresticker, Shalom <
shalom.bresticker@intel.com> wrote:

> I ran the example on two simulators.
>
...

> The other gave the following:
> 5 4 4 0
> 15 14 14 10
>

I believe the technical term for that behaviour is "wrong". It makes no
sense for input#10 to yield the signal's value as it was #5 in the past.

However, I would suggest that Daniel's example is methodologically flawed
(although it's an interesting example): if you are using a skew larger than
#1step, then presumably you are doing so precisely because you want to
sample the signals at a time when they are stable. But Daniel's example
samples 'a' at a timestep in which it changes. This is a nice test for tool
compliance (the sampling should be done in Postponed, and therefore should
reliably give the settled $strobe-like value of 'a' in that timestep) but
doesn't make much sense in practice.

Jonathan Bromley

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Received on Thu Jun 23 03:33:56 2011

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