RE: [sv-ec] transition coverpoints and iff

“The expression within the iff construct specifies an optional condition that disables coverage for that coverpoint.
If the guard expression evaluates to false at a sampling point, the coverage point is ignored.”

I interpret “ignored” to mean as if no sample() had occurred: 1)

You are perceptive to point out that the behavior of a reset should really be similar to that of a property’s disable construct. But I would prefer to keep transition bins simple and leave anything more complex to a cover directive.


Dave
Mentor Graphics

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Daniel Mlynek
Sent: Thursday, September 05, 2013 6:11 AM
To: sv-ec@eda.org
Subject: [sv-ec] transition coverpoints and iff

LRM do not explains for iff should behave for transition coverpoints. I see at least 2 options - when iff condition is false at the moment of sampling:
1. skip this sample
2. kill whole transition sequence
There could be also 3rd possibility that iff is async but it rather wont be compatybily with other covergroup features.

Am I missing the description of this feature?
How it should work?
Should I report mantis on that?

Consider example should "b" be covered or not (for 1st solution it should be for 2nd it should not)
module top;
    int i,i1,i2,i3,i4,i5;
    bit r;
    covergroup CG;
        type_option.merge_instances = 1;
        coverpoint i4 iff(!r){
            bins b = (1=>2=>3);
        }
    endgroup
     CG cg = new;
     initial begin
        i4=0;r=0;
         #1;cg.sample;#1;
        i4=1;r=0;
         #1;cg.sample;#1;
        i4=10;r=1;//here iff condition is tunred off
         #1;cg.sample;#1;
        i4=2;r=0;
         #1;cg.sample;#1;
        i4=3;r=0;
         #1;cg.sample;#1;
    end
endmodule

DANiel

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