RE: [sv-ec] Packed union member pass by reference

Ok. So workaroud for this problem is to use whole union.
Thanks for Your answer,
Radek

  _____  

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Thursday, December 05, 2013 10:29 AM
To: Radosław Nawrot; sv-ec@eda.org
Subject: RE: [sv-ec] Packed union member pass by reference



It would be the same for a select of a vector.

I think the reason is that allowing it would harm performance.

Shalom

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Rados?aw
Nawrot
Sent: Thursday, December 05, 2013 09:43
To: sv-ec@eda.org
Subject: [sv-ec] Packed union member pass by reference

Hi,

I have question about packed union elements pass by reference.

Simple example:

module top (  );
 union packed {reg r; bit b;}u;
 function  automatic void foo(ref reg x);
  x=1'bz;
 endfunction
 task automatic tsk (ref bit b);
 #1;
 case ( b )
  0: $display("0");
  1: $display("1");
  default : $display("Error");
 endcase
 endtask
 
 initial
  fork
   foo(u.r);
   tsk(u.b);
  join
endmodule

LRM say's:"

Only the following shall be legal to pass by reference:

- A variable,

- A class property,

- A member of an unpacked structure, or

- An element of an unpacked array.

"

That means union member cannot be passed by reference. Am I right?  Why?

What are the contraindications to allow such construction?

Regards,

Radek


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