[sv-ec] FW: [sv-bc] Name of processes

From: Bresticker, Shalom <shalom.bresticker@intel.com>
Date: Wed May 07 2014 - 04:33:25 PDT
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Rados?aw Nawrot
Sent: Wednesday, May 07, 2014 11:20
To: 'SV_BC List'
Subject: [sv-bc] Name of processes

Hi,
It there any way to name process like always or initial ?
In my design,  body of many processes are changing while development. It would be nice to give them names which can be obtain in simulator (I'm not talking about comments) i.e in User interface or receive vpiName from vpiProcess
I know that I can name begin-end block but this is not actually the same thing.

simple example :

state_trigg: always @(posedge clk)
                 state<=next_state;

It would be nice to have such feature in standard

Best regards ,
Radek

--
This message has been scanned for viruses and
dangerous content by MailScanner<http://www.mailscanner.info/>, and is
believed to be clean.
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.
Received on Wed May 7 04:33:53 2014

This archive was generated by hypermail 2.1.8 : Wed May 07 2014 - 04:34:19 PDT