SV-EC
			Agenda
			28 June 2002

Overview:

1. Setup
2. Committee mission
3. Goals/Objectives
4. Process
5. Milestones
6. Deliverables

Details:

1. Setup:
	Get scribe
	Take role/establish committee members
	Announce co-chair
	email reflector: sv-ec@eda.org
	website: http://www.eda.org/vlog-pp/sv-ec

2. Committee Mission
    A. Review SV-Enhacenment Committee formation definition
	Focus on the enhancement and focused area of donations. The only
	new donation we have is Synopsys. In addition to the committee
	list we have the TestBench from Synopsys.

    B. Establish Mission (based on the formation definition)
	Development System Verilog 3.1 LRM based on clean-up and extensions.
	Process any extensions provided to the committee by the TCC chair.

    May be modified Based on discussion during call.

3. Goals/Objectives
    A. Resolve the open list of System Verilog 3.1 extensions.
    B. Process the Synopsys VeraLite TestBench donation
    C. Rationalize the the TestBench extensions with System Verilog as
	appropriate

4. Process

    Meeting schedule:
	Every 2 weeks starting 8 July 2002 from 11:00am (PDT) to 1:00pm.
	    8, 22 July
	    5, 19 August
	    2, 16, 30 September
	    14, 28 October
	    11, 25 November
	    9, 16 December
	    6, 20 January
	    3, 17 February

    The basic process is to review, evaluate, vote, and then LRM development
    for all activities.

    A. Item List
    	For each of the listed extensions:
	    i. Find advocate (today!) and assign milestone for completion
	    ii. Advocate develops proposal that includes:
		Problem statement - requirements to be met
		Analysis - Describe issues raised by the requirement and
		    interactions with the 3.0 LRM
		Solution statement - Describe syntax, semantics, and examples
		    for the proposed solution
	    iii. SV-EC reviews proposal and votes to proceed or table
	    iv. If vote is to proceed then develop LRM modifications, including
		BNF.
	    v. Committee votes on LRM modifications
	Consolidate all SV-BC and SV_EC LRM modifications into single document
	Committe votes on overal LRM to submit to parent committee/board

	Items in extension list are:
	    i. Data channels
	    ii. Pointers
	    iii. Force/release with strengths
	    iv. FSM (original ESS donation)
	    v. Extern modules
	    vi. OO
	    vii. Data path (if donated by Cadence)
	    viii. Alias
	    ix. Inherited declarations
	    x. Multi-clock FSM
	    xi. Inferred reg types

    B. Donation
    	Must analyze, evaluate, and accept or reject the donation through a
	formal vote.
	Draft LRM after donation accpetance by technical committee.

	i. Review all 8 chapters of donation. Purpose is to analyze and
	    evaluate donation. During review develop list of issues
	    organized by:
	    a. missing information
	    b. inconsistent information within donation
	    c. conflicts with Verilog/System Verilog
	    d. items to be migrated to System Verilog
	
	ii. Resolve issues in categories a and b.
	iii. Vote on acceptance or rejection of the donation
	iv. Resolve issues in category c and migrate issues in category d
	    to extension list (as appropriate)
	v. Create LRM based on initial donation that follows the IEEE
	    Verilog style including BNF
	vi. Committe votes on overal LRM to submit to parent committee/board

    C. Voting structure and rules
	3/4 meetings must be attended
	Vote on technical issues will be a simple majority of all attendees
	    (not limited to one per company)
	All procedural and final (accept donation, LRM) approvals (other
	    items at the chair's discretion) will follow the one vote peru
	    company rule. Each company has a designate (with proxy support).
	    IEEE members, who are not an Accellera member or commercial
	    affiliation will have an indivdual vote as well.
	Subject to TCC chair change/approval

5. Milestones
    A. Review external milestones
	September 1 2002 (4 meetings from now):
	    Each issue item should have an assigned owner. The owner must
	    develop changes/proposed enhancement and obtain sub-committee
	    approval.

	    Donations should have been analyzed, evaluated, and voting complete.

	December 2002 (8 meetings after first milestone)
	    Draft of System Verilog 3.1 LRM (with SV-BC collaboration)
	    Draft of TestBench LRM (may be part of 3.1 LRM)

	February 15 2003 (5 meetings after first draft)
	    Final draft version to the Accellera board

    B. Establish committee milestones
	8 July		Chapters 1 and 2 of donation
			    Lexical, types, operators, expressions
			    Subroutines
			(any extension proposals scheduled)
	22 July		Chapters 3 and 4 of donation
			    Sequential control
			    Concurrency
			(any extension proposals scheduled)
	5 August	Chapters 5 and 6 of donation
			    Interfaces to DUT
			    Signal Operations
			(any extension proposals scheduled)
	19 August	Chapters 7 and 8 of donation
			    Class
			    Linked Lists
			(any extension proposals scheduled)
			Vote on donation and all completed proposals
	2 September - December
			Milestones TBD for LRM creation

6. Deliverables
	System Verilog 3.1 LRM
	TestBench LRM